Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40384 )
Change subject: soc/intel/xeon_sp/cpx: add FSP_S customization ......................................................................
Patch Set 11:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/40384/3/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/chip.c:
https://review.coreboot.org/c/coreboot/+/40384/3/src/soc/intel/xeon_sp/cpx/c... PS3, Line 574: microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", : CBFS_TYPE_MICROCODE, µcode_len);
we already load microcode in cpx_init_cpus(), why do we do it again here?
Done
https://review.coreboot.org/c/coreboot/+/40384/3/src/soc/intel/xeon_sp/cpx/c... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40384/3/src/soc/intel/xeon_sp/cpx/c... PS3, Line 56: intel_microcode_load_unlocked(*microcode);
why this is needed?
Removed.
-
Jonathan Zhang (Code Review)