Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 )
Change subject: util/spd_tools: Add LP5 support for ADL ......................................................................
Patch Set 6:
(2 comments)
File util/spd_tools/src/spd_gen/lp5.go:
https://review.coreboot.org/c/coreboot/+/58679/comment/27944892_2ef12d9d PS5, Line 18: DensityPerDieGb int Yes, LP5 only supports one channel per die. I believe dual channel dies were a new feature added in LP4 then removed again in LP5 to simplify the design.
From Section 2.2 of the LP5 spec:
LPDDR5/LPDDR5X SDRAM is a high-speed synchronous SDRAM device internally configured with 1 channel containing either 16 or 8 DQ signals.
https://review.coreboot.org/c/coreboot/+/58679/comment/3a75cf62_b6ef18e3 PS5, Line 221: TCKMinPs:
Is this the clock period in the command & address clock(CK) or the data clock(WCK)? I believe it is […]
Yes, this is the CK period. Based on the Intel advisory, this is how the MRC expects this field to be used for LP5. I've added a comment to the code explaining this and also explaining the calculation.
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Reka Norman (Code Review)