[S] Change in coreboot[master]: soc/amd/picasso: remove LIDS field from global NVS

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72183 )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/picasso: remove LIDS field from global NVS
......................................................................

soc/amd/picasso: remove LIDS field from global NVS

Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Picasso SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.

Signed-off-by: Felix Held 
Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/mainboard/google/zork/dsdt.asl
M src/soc/amd/picasso/acpi/globalnvs.asl
M src/soc/amd/picasso/include/soc/nvs.h
3 files changed, 32 insertions(+), 14 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl
index 62520b9..d715cde 100644
--- a/src/mainboard/google/zork/dsdt.asl
+++ b/src/mainboard/google/zork/dsdt.asl
@@ -17,6 +17,8 @@
    #include <acpi/dsdt_top.asl>
    #include <globalnvs.asl>

+	Name(LIDS, 0)
+
    /* Power state notification to ALIB */
    #include <pnot.asl>

diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index f616361..2d24b88 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -9,11 +9,10 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
    /* Miscellaneous */
-	LIDS,	8,	// 0x00 - LID State
-	CBMC,	32,	// 0x01 - 0x04 - coreboot Memory Console
-	PM1I,	64,	// 0x05 - 0x0c - System Wake Source - PM1 Index
-	GPEI,	64,	// 0x0d - 0x14 - GPE Wake Source
-	TMPS,	8,	// 0x15 - Temperature Sensor ID
-	TCRT,	8,	// 0x16 - Critical Threshold
-	TPSV,	8,	// 0x17 - Passive Threshold
+	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
+	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
+	TMPS,	8,	// 0x14 - Temperature Sensor ID
+	TCRT,	8,	// 0x15 - Critical Threshold
+	TPSV,	8,	// 0x16 - Passive Threshold
 }
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index aef4a97..c5821bb 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -14,13 +14,12 @@

struct __packed global_nvs {
    /* Miscellaneous */
-	uint8_t		lids; /* 0x00 - LID State */
-	uint32_t	cbmc; /* 0x01 - 0x04 - coreboot Memory Console */
-	uint64_t	pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */
-	uint64_t	gpei; /* 0x0d - 0x14 - GPE Wake Source */
-	uint8_t		tmps; /* 0x15 - Temperature Sensor ID */
-	uint8_t		tcrt; /* 0x16 - Critical Threshold */
-	uint8_t		tpsv; /* 0x17 - Passive Threshold */
+	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
+	uint8_t		tmps; /* 0x14 - Temperature Sensor ID */
+	uint8_t		tcrt; /* 0x15 - Critical Threshold */
+	uint8_t		tpsv; /* 0x16 - Passive Threshold */
 };

#endif /* AMD_PICASSO_NVS_H */