Change in coreboot[master]: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41862 )

Change subject: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax
......................................................................

soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax

This change updates scs.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f
Signed-off-by: V Sowmya 
---
M src/soc/intel/jasperlake/acpi/scs.asl
1 file changed, 12 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41862/1

diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl
index bee862d..508fb9b 100644
--- a/src/soc/intel/jasperlake/acpi/scs.asl
+++ b/src/soc/intel/jasperlake/acpi/scs.asl
@@ -37,22 +37,22 @@
    	Method(_PS0, 0, Serialized) {
    		Stall (50) // Sleep 50 us

-			Store(0, PGEN) // Disable PG
+			PGEN = 0 // Disable PG

/* Clear register 0x1C20/0x4820 */
    		SCSC (PID_EMMC)

/* Set Power State to D0 */
-			And (PMCR, 0xFFFC, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR & 0xFFFC
+			TEMP = PMCR
    	}

Method(_PS3, 0, Serialized) {
-			Store(1, PGEN) // Enable PG
+			PGEN = 1 // Enable PG

/* Set Power State to D3 */
-			Or (PMCR, 0x0003, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR | 0x0003
+			TEMP = PMCR
    	}

Device (CARD)
@@ -90,23 +90,23 @@

Method (_PS0, 0, Serialized)
    	{
-			Store (0, PGEN) /* Disable PG */
+			PGEN = 0 /* Disable PG */

/* Clear register 0x1C20/0x4820 */
    		SCSC (PID_SDX)

/* Set Power State to D0 */
-			And (PMCR, 0xFFFC, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR & 0xFFFC
+			TEMP = PMCR
    	}

Method (_PS3, 0, Serialized)
    	{
-			Store (1, PGEN) /* Enable PG */
+			PGEN = 1 /* Enable PG */

/* Set Power State to D3 */
-			Or (PMCR, 0x0003, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR | 0x0003
+			TEMP = PMCR
    	}

Device (CARD)

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41862 )

Change subject: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax
......................................................................

Patch Set 1: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41862 )

Change subject: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax
......................................................................

Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/41862/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/41862/1//COMMIT_MSG@7 
PS1, Line 7: Updat
update

Change in coreboot[master]: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Selma Bensaid, Subrata Banik, Arthur Heymans, Alexey Buyanov, Patrick Rudolph, Venkata Krishna Nimmagadda,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41862

to look at the new patch set (#2).

Change subject: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax
......................................................................

soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax

This change updates scs.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f
Signed-off-by: V Sowmya 
---
M src/soc/intel/jasperlake/acpi/scs.asl
1 file changed, 12 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41862/2

Change in coreboot[master]: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41862 )

Change subject: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax
......................................................................

Patch Set 2:

(1 comment)
> Patch Set 1: Code-Review+2
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/41862/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/41862/1//COMMIT_MSG@7 
PS1, Line 7: Updat
> update

Done

Change in coreboot[master]: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41862 )

Change subject: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax
......................................................................

soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax

This change updates scs.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f
Signed-off-by: V Sowmya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41862
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/jasperlake/acpi/scs.asl
1 file changed, 12 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl
index bee862d..508fb9b 100644
--- a/src/soc/intel/jasperlake/acpi/scs.asl
+++ b/src/soc/intel/jasperlake/acpi/scs.asl
@@ -37,22 +37,22 @@
    	Method(_PS0, 0, Serialized) {
    		Stall (50) // Sleep 50 us

-			Store(0, PGEN) // Disable PG
+			PGEN = 0 // Disable PG

/* Clear register 0x1C20/0x4820 */
    		SCSC (PID_EMMC)

/* Set Power State to D0 */
-			And (PMCR, 0xFFFC, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR & 0xFFFC
+			TEMP = PMCR
    	}

Method(_PS3, 0, Serialized) {
-			Store(1, PGEN) // Enable PG
+			PGEN = 1 // Enable PG

/* Set Power State to D3 */
-			Or (PMCR, 0x0003, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR | 0x0003
+			TEMP = PMCR
    	}

Device (CARD)
@@ -90,23 +90,23 @@

Method (_PS0, 0, Serialized)
    	{
-			Store (0, PGEN) /* Disable PG */
+			PGEN = 0 /* Disable PG */

/* Clear register 0x1C20/0x4820 */
    		SCSC (PID_SDX)

/* Set Power State to D0 */
-			And (PMCR, 0xFFFC, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR & 0xFFFC
+			TEMP = PMCR
    	}

Method (_PS3, 0, Serialized)
    	{
-			Store (1, PGEN) /* Enable PG */
+			PGEN = 1 /* Enable PG */

/* Set Power State to D3 */
-			Or (PMCR, 0x0003, PMCR)
-			Store (PMCR, TEMP)
+			PMCR = PMCR | 0x0003
+			TEMP = PMCR
    	}

Device (CARD)

Change in coreboot[master]: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41862 )

Change subject: soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4644
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4643
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4642
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4641

Please note: This test is under development and might not be accurate at all!