New patch to review for coreboot: gru: include ram_code in coreboot table

[Martin Roth]

Martin Roth ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15566

-gerrit

commit 8779acee43915761a1778e13963a2fd8349a7b2b
Author: Vadim Bendebury 
Date:   Tue Jun 21 19:07:32 2016 -0700

gru: include ram_code in coreboot table

This is needed to ensure that the ram-code node is included in the
    device tree by depthcharge.

BRANCH=none
    BUG=chrome-os-partner:54566
    TEST=built updated firmware, booted on kevin into Linux shell, checked
         the device tree contents:

localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code
      0000000 00 00 00 01
      0000004
      localhost #

Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b
    Signed-off-by: Martin Roth 
    Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f
    Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed
    Original-Signed-off-by: Vadim Bendebury 
    Original-Reviewed-on: https://chromium-review.googlesource.com/354705
    Original-Reviewed-by: Aaron Durbin 
---
 src/mainboard/google/gru/Kconfig         |  1 +
 src/mainboard/google/gru/Makefile.inc    |  1 +
 src/mainboard/google/gru/boardid.c       |  5 -----
 src/mainboard/google/gru/sdram_configs.c | 22 ++++++++++++++++------
 4 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index 170e358..1b42059 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
    select MAINBOARD_DO_NATIVE_VGA_INIT
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select RAM_CODE_SUPPORT
    select RTC
    select SOC_ROCKCHIP_RK3399
    select SPI_FLASH
diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc
index a209d1b..9e87fad 100644
--- a/src/mainboard/google/gru/Makefile.inc
+++ b/src/mainboard/google/gru/Makefile.inc
@@ -33,3 +33,4 @@ ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += memlayout.ld
 ramstage-y += reset.c
+ramstage-y += sdram_configs.c  # Needed for ram_code()
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index 1d37a86..b0c1eaf 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -59,8 +59,3 @@ uint8_t board_id(void)
           adc_reading);
    return 0;
 }
-
-uint32_t ram_code(void)
-{
-	return 0;
-}
diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c
index 92e00ef..f1f889c 100644
--- a/src/mainboard/google/gru/sdram_configs.c
+++ b/src/mainboard/google/gru/sdram_configs.c
@@ -38,19 +38,29 @@ enum dram_speeds {
 /*	dram_928MHz = 4, */
 };

-const struct rk3399_sdram_params *get_sdram_config()
+static enum dram_speeds get_sdram_index(void)
 {
-	enum dram_speeds speed;
-
    if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
-		speed = dram_300MHz;
+		return dram_300MHz;
    else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
-		speed = dram_800MHz;
+		return dram_800MHz;
    else
-		speed = dram_200MHz;
+		return dram_200MHz;
+}
+
+const struct rk3399_sdram_params *get_sdram_config()
+{
+
+	enum dram_speeds speed = get_sdram_index();

printk(BIOS_INFO, "Using SDRAM configuration for %d MHz\n",
           sdram_configs[speed].ddr_freq / (1000 * 1000));

return &sdram_configs[speed];
 }
+
+
+uint32_t ram_code(void)
+{
+	return get_sdram_index();
+}