Patch set updated for coreboot: Allow to add a second bootblock at a 64K offset for BUC.TS

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18148

-gerrit

commit 11b7b385bf68b69fe9266dd8095075a281c4b37a
Author: Arthur Heymans 
Date:   Sun Jan 15 14:24:56 2017 +0100

Allow to add a second bootblock at a 64K offset for BUC.TS

This allows to add a second bootblock at an offset of 64K in order for
    it to be used if the BUC.TS bit, RCBA(0x3414)[BIT0], is set.

This method is often used to flash coreboot when the vendor BIOS only
    write protects its bootblock at the bottom of flash (e.g. Lenovo
    thinkpad X60 and T60), but can also be used to have a backup while
    hacking on bootblock code.

TESTED on Thinkpad x200 with BIT0 of RCBA(0x3410) unset (not default
    in coreboot).

Change-Id: I37e288e710edbe41651d09d2a6981a571df69bde
    Signed-off-by: Arthur Heymans 
---
 Makefile.inc                           |  7 +++++++
 src/southbridge/intel/common/Kconfig   | 18 ++++++++++++++++++
 src/southbridge/intel/i82801gx/Kconfig |  1 +
 src/southbridge/intel/i82801ix/Kconfig |  1 +
 4 files changed, 27 insertions(+)

diff --git a/Makefile.inc b/Makefile.inc
index c5ce30f..d35e6b0 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -844,6 +844,13 @@ ifeq ($(CONFIG_ARCH_X86),y)
    	-n bootblock \
    	-t bootblock \
    	-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes)
+ifeq ($(CONFIG_BUCTS_BOOTBLOCK),y)
+	$(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock_bucts \
+		-t bootblock \
+		-b -$(call int-add,$(call file-size,$(objcbfs)/bootblock.bin) $(CONFIG_BUC_TOP_SWAP_SIZE)) $(cbfs-autogen-attributes)
+endif # ifeq CONFIG_BUCTS_BOOTBLOCK
 else # ifeq ($(CONFIG_ARCH_X86),y)
    $(CBFSTOOL) $@.tmp write -u \
    	-r BOOTBLOCK \
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 7bc686d..a651c80 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -2,3 +2,21 @@ config SOUTHBRIDGE_INTEL_COMMON
    def_bool n
 config SOUTHBRIDGE_INTEL_COMMON_GPIO
    def_bool n
+config HAVE_BUCTS
+	bool
+	default n
+config BUCTS_BOOTBLOCK
+	bool "Include a BUC.TS bootblock"
+	default n
+	depends on HAVE_BUCTS
+	help
+	  Some vendor BIOS only write protect their bootblock.
+	  Using the buc.ts register RCBA[0x3414], it is possible to have
+	  the southbridge look for the bootblock at a 64K offset
+	  instead of the usual top of flash, which might not be
+	  write protected.
+	  Select this to put a 'second' bootblock at a 64K offset.
+config BUC_TOP_SWAP_SIZE
+	hex
+	depends on BUCTS_BOOTBLOCK
+	default 0x10000
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index b2265c4..4eb2835 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
    select HAVE_SMI_HANDLER
    select COMMON_FADT
    select SOUTHBRIDGE_INTEL_COMMON_GPIO
+	select HAVE_BUCTS

if SOUTHBRIDGE_INTEL_I82801GX

diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index e4d1f91..0928a8a 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -25,6 +25,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
    select HAVE_USBDEBUG_OPTIONS
    select SOUTHBRIDGE_INTEL_COMMON_GPIO
    select HAVE_INTEL_FIRMWARE
+	select HAVE_BUCTS

if SOUTHBRIDGE_INTEL_I82801IX