Change in coreboot[master]: soc/amd/common/block/rtd3: Add AMD specific RTD3 driver

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 )

Change subject: soc/amd/common/block/rtd3: Add AMD specific RTD3 driver
......................................................................

Patch Set 1:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/54966/comment/3ddca407_c92c487c 
PS1, Line 9:  I decided
           : to copy and modify it because the Intel driver has a lot of Intel
           : specific code.
> From a quick look, I see that the following things were omitted: […]

I warned you Raul 😉

File src/soc/amd/common/block/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/54966/comment/9a756fa6_314945c1 
PS1, Line 23: static void pcie_rtd3_acpi_method_on(const struct soc_amd_common_block_rtd3_config *config)
            : {
            : 	acpigen_write_method_serialized("_ON", 0);
            : 
            : 	/* Assert enable GPIO to turn on device power. */
            : 	if (config->enable_gpio.pin_count) {
            : 		acpigen_enable_tx_gpio(&config->enable_gpio);
            : 		if (config->enable_delay_ms)
            : 			acpigen_write_sleep(config->enable_delay_ms);
            : 	}
            : 
            : 	/* De-assert reset GPIO to bring device out of reset. */
            : 	if (config->reset_gpio.pin_count) {
            : 		acpigen_disable_tx_gpio(&config->reset_gpio);
            : 		if (config->reset_delay_ms)
            : 			acpigen_write_sleep(config->reset_delay_ms);
            : 	}
            : 
            : 	acpigen_write_method_end();
            : }
            : 
            : static void pcie_rtd3_acpi_method_off(const struct soc_amd_common_block_rtd3_config *config)
            : {
            : 	acpigen_write_method_serialized("_OFF", 0);
            : 
            : 	/* Assert reset GPIO to place device into reset. */
            : 	if (config->reset_gpio.pin_count) {
            : 		acpigen_enable_tx_gpio(&config->reset_gpio);
            : 		if (config->reset_off_delay_ms)
            : 			acpigen_write_sleep(config->reset_off_delay_ms);
            : 	}
            : 
            : 	/* De-assert enable GPIO to turn off device power. */
            : 	if (config->enable_gpio.pin_count) {
            : 		acpigen_disable_tx_gpio(&config->enable_gpio);
            : 		if (config->enable_off_delay_ms)
            : 			acpigen_write_sleep(config->enable_off_delay_ms);
            : 	}
            : 
            : 	acpigen_write_method_end();
            : }
It's also on my todo-list to clean up the power resources to use acpigen and a separate device/chip...

https://review.coreboot.org/c/coreboot/+/54966/comment/a3ce46ba_3a1edcf2 
PS1, Line 206: PXSX
> So I shot a message to the LKML yesterday asking if we could remove this hardcoded constant: https:/ […]

Thanks Raul!

https://review.coreboot.org/c/coreboot/+/54966/comment/43ddee71_2c1e0cd9 
PS1, Line 210: pci_dev_read_resources
> Ah, are you envisioning a case where we have a bridge connected to the root port?  […]

That would require 2 of these fake devices for Intel then, wouldn't it?