Change in coreboot[master]: [WIP] intel/fsp2_0: Restrict references to CAR

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35289 )

Change subject: [WIP] intel/fsp2_0: Restrict references to CAR
......................................................................

[WIP] intel/fsp2_0: Restrict references to CAR

Change-Id: Ifb1e33d67722db086d9f9feff0e1d289f40d4ef5
Signed-off-by: Kyösti Mälkki 
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 21 insertions(+), 23 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35289/1

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index a916c9d..a4c7c07 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -185,24 +185,9 @@
    return CB_SUCCESS;
 }

-static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
-					bool s3wake, uint32_t fsp_version,
-					const struct memranges *memmap)
+static void cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
+					bool s3wake, uint32_t fsp_version)
 {
-	/*
-	 * FSP 2.1 version would use same stack as coreboot instead of
-	 * setting up separate stack frame. FSP 2.1 would not relocate stack
-	 * top and does not reinitialize stack pointer. The parameters passed
-	 * as StackBase and StackSize are actually for temporary RAM and HOBs
-	 * and are not related to FSP stack at all.
-	 */
-	if (CONFIG(FSP_USES_CB_STACK)) {
-		arch_upd->StackBase = temp_ram;
-		arch_upd->StackSize = sizeof(temp_ram);
-	} else if (setup_fsp_stack_frame(arch_upd, memmap)) {
-		return CB_ERR;
-	}
-
    fsp_fill_mrc_cache(arch_upd, fsp_version);

/* Configure bootmode */
@@ -226,8 +211,6 @@
    }

printk(BIOS_SPEW, "bootmode is set to :%d\n", arch_upd->BootMode);
-
-	return CB_SUCCESS;
 }

__weak
@@ -292,11 +275,23 @@
    /* Reserve enough memory under TOLUD to save CBMEM header */
    arch_upd->BootLoaderTolumSize = cbmem_overhead_size();

-	/* Fill common settings on behalf of chipset. */
-	if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
-					memmap) != CB_SUCCESS)
+	/*
+	 * FSP 2.1 version would use same stack as coreboot instead of
+	 * setting up separate stack frame. FSP 2.1 would not relocate stack
+	 * top and does not reinitialize stack pointer. The parameters passed
+	 * as StackBase and StackSize are actually for temporary RAM and HOBs
+	 * and are not related to FSP stack at all.
+	 */
+	if (CONFIG(FSP_USES_CB_STACK)) {
+		arch_upd->StackBase = temp_ram;
+		arch_upd->StackSize = sizeof(temp_ram);
+	} else if (setup_fsp_stack_frame(arch_upd, memmap)) {
    	die_with_post_code(POST_INVALID_VENDOR_BINARY,
    		"FSPM_ARCH_UPD not found!\n");
+	}
+
+	/* Fill common settings on behalf of chipset. */
+	fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version);

/* Give SoC and mainboard a chance to update the UPD */
    platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
@@ -421,7 +416,10 @@
    /* Signal that FSP component has been loaded. */
    prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL);

-	do_fsp_memory_init(&hdr, s3wake, &memmap);
+	if (CONFIG(FSP_USES_CB_STACK))
+		do_fsp_memory_init(&hdr, s3wake, NULL);
+	else
+		do_fsp_memory_init(&hdr, s3wake, &memmap);

timestamp_add_now(TS_AFTER_INITRAM);
 }