[S] Change in coreboot[master]: nb/intel/i945: Clean up includes

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68211 )

Change subject: nb/intel/i945: Clean up includes
......................................................................

nb/intel/i945: Clean up includes

Signed-off-by: Elyes Haouas 
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
---
M src/northbridge/intel/i945/errata.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/i945/romstage.c
4 files changed, 19 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/68211/1

diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c
index 3057ae9..c4219d9 100644
--- a/src/northbridge/intel/i945/errata.c
+++ b/src/northbridge/intel/i945/errata.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <stdint.h>
+
 #include "i945.h"
 #include "raminit.h"

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index d8993ac..3470a77 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -3,10 +3,11 @@
 #ifndef NORTHBRIDGE_INTEL_I945_H
 #define NORTHBRIDGE_INTEL_I945_H

-#define DEFAULT_X60BAR		0xfed13000
-
+#include <northbridge/intel/common/fixed_bars.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

+#define DEFAULT_X60BAR		0xfed13000
+
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__

@@ -86,12 +87,6 @@
 #define BSM		0x5c
 #define GCFC		0xf0	/* Graphics Clock Frequency & Gating Control */

-/*
- * MCHBAR
- */
-
-#include <northbridge/intel/common/fixed_bars.h>
-
 /* Chipset Control Registers */
 #define FSBPMC3		0x40	/* 32bit */
 #define FSBPMC4		0x44	/* 32bit */
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 513984f..33652b2 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -3,6 +3,8 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H

+#include <stdint.h>
+
 #define DIMM_SOCKETS 2

#define DIMM_TCO_BASE 0x30
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index 0a61780..61b9bcf 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <stdint.h>
-#include <cf9_reset.h>
 #include <arch/romstage.h>
+#include <cf9_reset.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/pmclib.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <stdint.h>

__weak void mainboard_lpc_decode(void)
 {