Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Support CL > 11

the following patch was just integrated into master:
commit 2966c9958985ed5a856f9aa6cfdb6dfa45ea8bf9
Author: Patrick Rudolph 
Date:   Sat Nov 19 15:46:42 2016 +0100

nb/intel/sandybridge/raminit: Support CL > 11

The code won't allow anything beyond CL11 due to short
    CAS Latency mask and a bug in mr0 which had the wrong
    bit set for CL > 11.

Increase the CAS bitmask, fix the mr0 reg to allow CAS Latencies
    from CL 5 to CL 18.
    Use defines instead of hardcoding min and max CAS latencies.

Tested on X220 with two 1866 MHz, CL13 memories
    Tested-By: Nicola Corna

Change-Id: I576ee20a923fd63d360a6a8e86c675dd069d53d6
    Signed-off-by: Patrick Rudolph 
    Reviewed-on: https://review.coreboot.org/17502
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin 
    Reviewed-by: Kyösti Mälkki

See https://review.coreboot.org/17502 for details.

-gerrit