[S] Change in coreboot[master]: soc/amd/picasso: use CPUID_FROM_FMS macro instead of magic numbers

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72857 )

Change subject: soc/amd/picasso: use CPUID_FROM_FMS macro instead of magic numbers
......................................................................

soc/amd/picasso: use CPUID_FROM_FMS macro instead of magic numbers

TEST=Resulting image of timeless build for Mandolin doesn't change.

Signed-off-by: Felix Held 
Change-Id: I44cb7759206e9e1ce79fd57f62b9a844e52f7394
---
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/include/soc/cpu.h
M src/soc/amd/picasso/soc_util.c
3 files changed, 23 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/72857/1

diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 5d206e4..1268543 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -48,9 +48,9 @@
 };

static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, RAVEN1_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
-	{ X86_VENDOR_AMD, PICASSO_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
-	{ X86_VENDOR_AMD, RAVEN2_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, RAVEN1_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, PICASSO_CPUID, CPUID_ALL_STEPPINGS_MASK },
+	{ X86_VENDOR_AMD, RAVEN2_CPUID, CPUID_ALL_STEPPINGS_MASK },
    { 0, 0, 0 },
 };

diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 7051bb8..07d0759 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -3,11 +3,9 @@
 #ifndef AMD_PICASSO_CPU_H
 #define AMD_PICASSO_CPU_H

-#define RAVEN1_B0_CPUID			0x00810f10
-#define PICASSO_B0_CPUID		0x00810f80
-#define PICASSO_B1_CPUID		0x00810f81
-#define RAVEN2_A0_CPUID			0x00820f00
-#define RAVEN2_A1_CPUID			0x00820f01
+#define RAVEN1_CPUID		CPUID_FROM_FMS(0x17, 0x11, 0)
+#define PICASSO_CPUID		CPUID_FROM_FMS(0x17, 0x18, 0)
+#define RAVEN2_CPUID		CPUID_FROM_FMS(0x17, 0x20, 0)

#define RAVEN1_VBIOS_VID_DID		0x100215dd
 #define RAVEN1_VBIOS_REV		0x81
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c
index 9616f26..bee42ac 100644
--- a/src/soc/amd/picasso/soc_util.c
+++ b/src/soc/amd/picasso/soc_util.c
@@ -94,31 +94,31 @@
 static bool is_fam17_1x(void)
 {
    /* mask lower model number nibble and stepping */
-	return cpuid_eax(1) >> 8 == PICASSO_B1_CPUID >> 8;
+	return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8;
 }

static bool is_fam17_11(void)
 {
    /* only mask stepping */
-	return cpuid_eax(1) >> 4 == RAVEN1_B0_CPUID >> 4;
+	return cpuid_eax(1) >> 4 == RAVEN1_CPUID >> 4;
 }

static bool is_fam17_18(void)
 {
    /* only mask stepping */
-	return cpuid_eax(1) >> 4 == PICASSO_B1_CPUID >> 4;
+	return cpuid_eax(1) >> 4 == PICASSO_CPUID >> 4;
 }

static bool is_fam17_2x(void)
 {
    /* mask lower model number nibble and stepping */
-	return cpuid_eax(1) >> 8 == RAVEN2_A1_CPUID >> 8;
+	return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8;
 }

static bool is_fam17_20(void)
 {
    /* only mask stepping */
-	return cpuid_eax(1) >> 4 == RAVEN2_A1_CPUID >> 4;
+	return cpuid_eax(1) >> 4 == RAVEN2_CPUID >> 4;
 }

enum silicon_type get_silicon_type(void)