Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30383
Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ......................................................................
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock. Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch.
Untested
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c D src/soc/intel/broadwell/bootblock/timestamp.inc M src/soc/intel/broadwell/romstage/Makefile.inc M src/soc/intel/broadwell/romstage/romstage.c 8 files changed, 36 insertions(+), 105 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/1
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index e6cbd95..8f77930 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -42,6 +42,8 @@ select INTEL_GMA_ACPI select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CONSOLE
config PCIEXP_ASPM bool @@ -66,18 +68,6 @@ config VBOOT select VBOOT_STARTS_IN_ROMSTAGE
-config BOOTBLOCK_CPU_INIT - string - default "soc/intel/broadwell/bootblock/cpu.c" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/systemagent.c" - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/pch.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 @@ -120,6 +110,13 @@ help The amount of cache-as-ram region required by the reference code.
+config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a Memory Reference Code binary" help diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index caf963c..70d8e39 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,13 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common
+bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/systemagent.c +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 7508bc2..52be618 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -19,48 +19,10 @@ #include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> -#include <cpu/intel/microcode/microcode.c> #include <soc/rcba.h> #include <soc/msr.h> - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void bootblock_mdelay(int ms) -{ - u32 target = ms * 24 * 1000; - msr_t current; - msr_t start = rdmsr(MSR_COUNTER_24_MHZ); - - do { - current = rdmsr(MSR_COUNTER_24_MHZ); - } while ((current.lo - start.lo) < target); -} +#include <delay.h> +#include <cpu/intel/car/bootblock.h>
static void set_flex_ratio_to_tdp_nominal(void) { @@ -103,7 +65,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1);
/* Delay before reset to avoid potential TPM lockout */ - bootblock_mdelay(30); + mdelay(30);
/* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); @@ -126,11 +88,9 @@ } }
-static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 2643801..9cd199f 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,6 +19,7 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/spi.h> +#include <cpu/intel/car/bootblock.h>
/* * Enable Prefetching and Caching. @@ -66,7 +67,7 @@ SPIBAR8(SPIBAR_SSFC + 2) = ssfc; }
-static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 1a09f8e..61fc8c2 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -16,8 +16,9 @@ #include <arch/io.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <cpu/intel/car/bootblock.h>
-static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg;
diff --git a/src/soc/intel/broadwell/bootblock/timestamp.inc b/src/soc/intel/broadwell/bootblock/timestamp.inc deleted file mode 100644 index 3115c22..0000000 --- a/src/soc/intel/broadwell/bootblock/timestamp.inc +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Store the initial timestamp for booting in mmx registers. This works - * because the bootblock isn't being compiled with MMX support so mm0 and - * mm1 will be preserved into romstage. - */ - .code32 - -.global stash_timestamp -stash_timestamp: - - /* Save the BIST value */ - movl %eax, %ebp - - finit - rdtsc - movd %eax, %mm0 - movd %edx, %mm1 - - /* Restore the BIST value to %eax */ - movl %ebp, %eax diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 2d562d9..60c8446 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,3 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S - romstage-y += cpu.c romstage-y += pch.c romstage-y += power_state.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index afc8216..8d75f50 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -63,19 +63,24 @@ run_postcar_phase(&pcf); }
-/* Entry from cache-as-ram.inc. */ -asmlinkage void *romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) +static inline int get_bist_result(void) +{ + int result; + asm ("movd %%mm0, %0;" + : "=r" (result)); + return result; +} + +asmlinkage void car_stage_entry(void) { struct romstage_params rp = { - .bist = bist, + .bist = get_bist_result(), .pei_data = NULL, };
- post_code(0x30); + console_init();
- /* Save initial timestamp from bootblock. */ - timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + post_code(0x30);
/* Save romstage begin */ timestamp_add_now(TS_START_ROMSTAGE); @@ -90,9 +95,6 @@ on IT8772 */ mainboard_pre_console_init();
- /* Start console drivers */ - console_init(); - /* Get power state */ rp.power_state = fill_power_state();
@@ -106,8 +108,6 @@ mainboard_romstage_entry(&rp);
platform_enter_postcar(); - - return NULL; }
/* Entry from the mainboard. */
-
Arthur Heymans (Code Review)