[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Paul Menzel, Raul Rangel.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email )

Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
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Patch Set 6:

(1 comment)

Patchset:

PS6: 
@Jonny, can I request you to pick CB:77616 and CB:77556 Cls and share your feedback.

I have verified the exclusive boot scenario related to xeon_sp where FSP-S populates the NVS data. Please take a look into the MRC cache write in successful post FSP-S.

```
First boot  | Post FSP-S

[DEBUG]  FMAP: area RW_MRC_CACHE found @ 1710000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x4000000
[ERROR]  SF size 0x4000000 does not correspond to CONFIG_ROM_SIZE 0x2000000!!
[NOTE ]  MRC: no data in 'RW_MRC_CACHE'
[DEBUG]  MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG]  MRC: updated 'RW_MRC_CACHE'.
[DEBUG]  FMAP: area RW_ELOG found @ 1720000 (16384 bytes)
[INFO ]  ELOG: NV offset 0x1720000 size 0x4000
[ERROR]  ELOG: NV Buffer Cleared.

consecutive boot | Post FSP-S

[DEBUG]  FMAP: area RW_MRC_CACHE found @ 1710000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x4000000
[ERROR]  SF size 0x4000000 does not correspond to CONFIG_ROM_SIZE 0x2000000!!
[DEBUG]  MRC: 'RW_MRC_CACHE' does not need update.

```