[S] Change in coreboot[main]: mb/siemens/mc_ehl5: Limit eMMC speed mode to DDR50

[Mario Scheithauer (Code Review)]

Attention is currently required from: Werner Zeh.

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85314?usp=email )

Change subject: mb/siemens/mc_ehl5: Limit eMMC speed mode to DDR50
......................................................................

mb/siemens/mc_ehl5: Limit eMMC speed mode to DDR50

Due to layout restrictions on mc_ehl5, the eMMC interface is limited to
operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the eMMC controller to DDR50 mode
only so that the eMMC driver in OS will choose the right mode for
operation even if the attached eMMC card supports higher modes.

BUG=none
TEST=Boot into Linux and check dmesg output for mmc modes

Change-Id: Ie3214bc3e25e7af706a5c96244d0be50f4bb3094
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85314/1

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
index a1ce64a..3632ab4 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
@@ -51,6 +51,22 @@
    	reg16 |= HOSTCTRL2_PRESET;
    	write16(res2mmio(res, HOSTCTRL2, 0), reg16);
    }
+
+	/* Limit eMMC speed to DDR50 mode to avoid SDR104/SDR50 modes due to
+	   layout limitations. */
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+	if (dev) {
+		uint32_t reg;
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (!res)
+			return;
+		write32(res2mmio(res, MMC_CAP_BYP, 0), MMC_CAP_BYP_EN);
+		reg = read32(res2mmio(res, MMC_CAP_BYP_REG1, 0));
+		/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */
+		reg &= ~(MMC_CAP_BYP_SDR104 | MMC_CAP_BYP_SDR50);
+		reg |= MMC_CAP_BYP_DDR50;
+		write32(res2mmio(res, MMC_CAP_BYP_REG1, 0), reg);
+	}
 }

static void finalize_boot(void *unused)