Change in ...coreboot[master]: soc/intel: Update mainboard UART Kconfig

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30853

Change subject: soc/intel: Update mainboard UART Kconfig
......................................................................

soc/intel: Update mainboard UART Kconfig

After 29573 get merged, all the mainboard using intel apollolake,
cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake
all get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of
UART_DEBUG and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao 
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
---
M src/mainboard/google/dragonegg/Kconfig
M src/mainboard/google/eve/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/reef/Kconfig
M src/mainboard/google/sarien/Kconfig
M src/mainboard/intel/apollolake_rvp/Kconfig
M src/mainboard/intel/cannonlake_rvp/Kconfig
M src/mainboard/intel/coffeelake_rvp/Kconfig
M src/mainboard/intel/glkrvp/Kconfig
M src/mainboard/intel/icelake_rvp/Kconfig
M src/mainboard/intel/kblrvp/Kconfig
M src/mainboard/intel/kunimitsu/Kconfig
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
M src/mainboard/siemens/mc_apl1/Kconfig
19 files changed, 70 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30853/1

diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig
index 18382d5..39228f4 100644
--- a/src/mainboard/google/dragonegg/Kconfig
+++ b/src/mainboard/google/dragonegg/Kconfig
@@ -8,6 +8,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select SOC_INTEL_ICELAKE

diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index 7c98339..f7fb9c6 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
@@ -75,4 +76,7 @@
    select NHLT_RT5663
    select NHLT_MAX98927

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 26f6f3a..1748d89 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_USES_FSP2_0
    select NO_FADT_8042
@@ -97,4 +98,7 @@
    select NHLT_DMIC_4CH
    select NHLT_MAX98357

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif # BOARD_GOOGLE_BASEBOARD_FIZZ
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 05572df..b75b726 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -13,6 +13,7 @@
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
    select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_LPC_TPM
    select MAINBOARD_HAS_TPM1
@@ -96,4 +97,8 @@
    default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
    default "LARS TEST 5001" if BOARD_GOOGLE_LARS
    default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY
+
+config UART_FOR_CONSOLE
+	int
+	default 2
 endif
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 214a1b6..1fe090f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -9,6 +9,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_SPI_TPM_CR50
    select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 15230dc..a237741 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -13,6 +13,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select SOC_ESPI
    select MAINBOARD_HAS_SPI_TPM_CR50
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index 59abe72..419b10e 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -10,6 +10,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_USES_FSP2_0
    select SOC_INTEL_KABYLAKE
@@ -214,4 +215,7 @@
    select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
    select VBOOT_LID_SWITCH

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif # BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 09b2e61..d2240a8 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -12,6 +12,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 5bf4824..ff2f678 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -11,6 +11,7 @@
    select GENERIC_SPD_BIN
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
@@ -82,6 +83,10 @@
    int
    default 8

+config UART_FOR_CONSOLE
+	int
+	default 2
+
 config VARIANT_DIR
    string
    default "arcada" if BOARD_GOOGLE_ARCADA
diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig
index 4afdf0d..ed7d77f 100644
--- a/src/mainboard/intel/apollolake_rvp/Kconfig
+++ b/src/mainboard/intel/apollolake_rvp/Kconfig
@@ -5,6 +5,7 @@
    select SOC_INTEL_APOLLOLAKE
    select BOARD_ROMSIZE_KB_8192
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE

config MAINBOARD_DIR
    string
@@ -18,4 +19,6 @@
    string
    default "Intel"

+config UART_FOR_CONSOLE
+	default 2
 endif
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig
index 15d56c3..4f5df99 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig
@@ -6,6 +6,7 @@
    select GENERIC_SPD_BIN
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select GENERIC_SPD_BIN
    select DRIVERS_I2C_HID
@@ -62,6 +63,10 @@
    int
    default 512

+config UART_FOR_CONSOLE
+	int
+	default 2
+
 config VBOOT
    select VBOOT_LID_SWITCH
    select VBOOT_MOCK_SECDATA
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 9474c51..a4fb2b8 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -7,6 +7,7 @@
    select GENERIC_SPD_BIN
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select GENERIC_SPD_BIN
    select DRIVERS_I2C_HID
@@ -81,4 +82,8 @@
 config VBOOT
    select VBOOT_LID_SWITCH
    select VBOOT_MOCK_SECDATA
+
+config UART_FOR_CONSOLE
+	int
+	default 0
 endif
diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig
index 9484559..ce43dcc 100644
--- a/src/mainboard/intel/glkrvp/Kconfig
+++ b/src/mainboard/intel/glkrvp/Kconfig
@@ -1,17 +1,18 @@

config BOARD_INTEL_BASEBOARD_GLKRVP
    def_bool n
-	select SOC_INTEL_GLK
    select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GENERIC_MAX98357A
+	select DRIVERS_I2C_DA7219
    select DRIVERS_I2C_GENERIC
    select DRIVERS_I2C_HID
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_LPC_TPM
-	select DRIVERS_GENERIC_MAX98357A
-	select DRIVERS_I2C_DA7219
    select SOC_ESPI
+	select SOC_INTEL_GLK

if BOARD_INTEL_BASEBOARD_GLKRVP

diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig
index da9c077..b08b24e 100644
--- a/src/mainboard/intel/icelake_rvp/Kconfig
+++ b/src/mainboard/intel/icelake_rvp/Kconfig
@@ -6,6 +6,7 @@
    select GENERIC_SPD_BIN
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select GENERIC_SPD_BIN
    select DRIVERS_I2C_HID
@@ -51,4 +52,8 @@
 config VBOOT
    select VBOOT_LID_SWITCH
    select VBOOT_MOCK_SECDATA
+
+config UART_FOR_CONSOLE
+	int
+	default 0
 endif
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index e385289..aa64edb 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -7,6 +7,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8
    select SOC_INTEL_SKYLAKE
    select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8
@@ -82,4 +83,8 @@
 config DIMM_SPD_SIZE
    int
    default 512 if BOARD_INTEL_KBLRVP8 #DDR4
+
+config UART_FOR_CONSOLE
+	int
+	default 0
 endif
diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig
index e2a6738..f4dd4b1 100644
--- a/src/mainboard/intel/kunimitsu/Kconfig
+++ b/src/mainboard/intel/kunimitsu/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_LPC_TPM
    select SOC_INTEL_SKYLAKE
@@ -72,4 +73,8 @@
    string
    depends on CHROMEOS
    default "KUNIMITSU TEST 8819"
+
+config UART_FOR_CONSOLE
+	int
+	default 2
 endif
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index c8113d2..b61d775 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -24,6 +24,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select SERIRQ_CONTINUOUS_MODE
    select SKYLAKE_SOC_PCH_H
    select SOC_INTEL_SKYLAKE
@@ -59,4 +60,6 @@
    hex
    default 0x18  # GPP_E0_IRQ

+config UART_FOR_CONSOLE
+	default 0
 endif
diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig
index d757d1a..402a575 100644
--- a/src/mainboard/purism/librem_skl/Kconfig
+++ b/src/mainboard/purism/librem_skl/Kconfig
@@ -4,6 +4,7 @@
    select BOARD_ROMSIZE_KB_16384
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select SOC_INTEL_SKYLAKE
    # Workaround for EC/KBC IRQ1
    select SERIRQ_CONTINUOUS_MODE
@@ -59,6 +60,10 @@
      This platform does not have any way to see POST codes
      so disable them by default.

+config UART_FOR_CONSOLE
+	int "Number of UART port to use for serial log"
+	default 0
+
 config VGA_BIOS_ID
    string
    default "8086,1916"
diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig
index 7ec843b..903d6c6 100644
--- a/src/mainboard/siemens/mc_apl1/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/Kconfig
@@ -4,6 +4,7 @@
    select SOC_INTEL_APOLLOLAKE
    select BOARD_ROMSIZE_KB_16384
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select USE_SIEMENS_HWILIB

source "src/mainboard/siemens/mc_apl1/variants/*/Kconfig"
@@ -38,4 +39,7 @@
    int
    default 8

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif # BOARD_SIEMENS_BASEBOARD_MC_APL1

[Lijian Zhao (Code Review)]

Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Nico Huber, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30853

to look at the new patch set (#2).

Change subject: soc/intel: Update mainboard UART Kconfig
......................................................................

soc/intel: Update mainboard UART Kconfig

After 29573 get merged, all the mainboard using intel apollolake,
cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake
all get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of
UART_DEBUG and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao 
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
---
M src/mainboard/google/dragonegg/Kconfig
M src/mainboard/google/eve/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/reef/Kconfig
M src/mainboard/google/sarien/Kconfig
M src/mainboard/intel/apollolake_rvp/Kconfig
M src/mainboard/intel/glkrvp/Kconfig
M src/mainboard/intel/kunimitsu/Kconfig
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
M src/mainboard/siemens/mc_apl1/Kconfig
15 files changed, 50 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30853/2

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/intel: Update mainboard UART Kconfig
......................................................................

Patch Set 2:

Skip big core RVP platform, as they are using legacy uart port over EC or superio.

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/intel: Update mainboard UART Kconfig
......................................................................

Patch Set 2:

(6 comments)

thanks :)

https://review.coreboot.org/#/c/30853/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30853/2//COMMIT_MSG@9 
PS2, Line 9: 29573
Please no Gerrit references. As the commit is already merged,
you can use its commit id, e.g.

After f5ca922 (Untangle CBFS microcode updates) got merged, ...

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig 
File src/mainboard/intel/glkrvp/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig@6 
PS2, Line 6: 	select DRIVERS_I2C_DA7219
Unrelated changes. I understand the urge to fix the order, but please
do it in a separate commit.

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/saddlebrook/Kcon... 
File src/mainboard/intel/saddlebrook/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/saddlebrook/Kcon... 
PS2, Line 64: 	default 0
Default is already 0, please remove.

https://review.coreboot.org/#/c/30853/2/src/mainboard/purism/librem_skl/Kcon... 
File src/mainboard/purism/librem_skl/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/purism/librem_skl/Kcon... 
PS2, Line 64: 	int "Number of UART port to use for serial log"
No prompts. The whole point of INTEL_LPSS_UART_FOR_CONSOLE is to
hide the potential dangerous prompt.

https://review.coreboot.org/#/c/30853/2/src/mainboard/purism/librem_skl/Kcon... 
PS2, Line 65: 	default 0
Oh, default is 0 anyway, so the whole block should be removed.

https://review.coreboot.org/#/c/30853/2/src/mainboard/siemens/mc_apl1/Kconfi... 
File src/mainboard/siemens/mc_apl1/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/siemens/mc_apl1/Kconfi... 
PS2, Line 43: 	int
I think this conflicts with CB:30836

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/intel: Update mainboard UART Kconfig
......................................................................

Patch Set 2:

(2 comments)

I just compared the settings here to `gpio.c` files. Found two oddities
in them. But that doesn't mean that something is wrong.

Generally, it would be much preferred to not have redundant configu-
rations. I only added INTEL_LPSS_UART_FOR_CONSOLE to guard the current
code that seems dangerous. Ideally we would get rid of that code and
use information from `gpio.c` files only (for the pad configuration).
We would still need UART_FOR_DEBUG to know which UART is actually used
for debugging.

https://review.coreboot.org/#/c/30853/2/src/mainboard/google/reef/Kconfig 
File src/mainboard/google/reef/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/google/reef/Kconfig@14 
PS2, Line 14: 	select HAVE_ACPI_TABLES
There is this comment in the gpio.c:

PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),      /* LPSS_UART0_TXD - unused */

`unused` could also mean it's only used for debugging. UART1 and
UART2 are used in gpio.c, are we sure about this?

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig 
File src/mainboard/intel/glkrvp/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig@1... 
PS2, Line 10: 	select HAVE_ACPI_TABLES
gpio.c enables UART2, though maybe for a different use case?

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Lijian Zhao (Code Review)]

Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Nico Huber, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30853

to look at the new patch set (#3).

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

soc/mainboard: Update mainboard UART Kconfig

After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG 
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao 
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
---
M src/mainboard/google/dragonegg/Kconfig
M src/mainboard/google/eve/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/reef/Kconfig
M src/mainboard/google/sarien/Kconfig
M src/mainboard/intel/apollolake_rvp/Kconfig
M src/mainboard/intel/glkrvp/Kconfig
M src/mainboard/intel/kunimitsu/Kconfig
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
14 files changed, 40 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30853/3

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Lijian Zhao (Code Review)]

Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Nico Huber, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30853

to look at the new patch set (#4).

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

soc/mainboard: Update mainboard UART Kconfig

After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG 
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao 
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
---
M src/mainboard/google/dragonegg/Kconfig
M src/mainboard/google/eve/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/reef/Kconfig
M src/mainboard/google/sarien/Kconfig
M src/mainboard/intel/apollolake_rvp/Kconfig
M src/mainboard/intel/glkrvp/Kconfig
M src/mainboard/intel/kunimitsu/Kconfig
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
14 files changed, 37 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30853/4

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

Patch Set 2:

(8 comments)

https://review.coreboot.org/#/c/30853/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30853/2//COMMIT_MSG@9 
PS2, Line 9: 29573
> Please no Gerrit references. As the commit is already merged, […]

Done

https://review.coreboot.org/#/c/30853/2/src/mainboard/google/reef/Kconfig 
File src/mainboard/google/reef/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/google/reef/Kconfig@14 
PS2, Line 14: 	select HAVE_ACPI_TABLES
> There is this comment in the gpio.c: […]

Yes, it already select UART2 in Kconfig

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig 
File src/mainboard/intel/glkrvp/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig@6 
PS2, Line 6: 	select DRIVERS_I2C_DA7219
> Unrelated changes. I understand the urge to fix the order, but please […]

Done

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/glkrvp/Kconfig@1... 
PS2, Line 10: 	select HAVE_ACPI_TABLES
> gpio. […]

Yes it did select UART2

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/saddlebrook/Kcon... 
File src/mainboard/intel/saddlebrook/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/intel/saddlebrook/Kcon... 
PS2, Line 64: 	default 0
> Default is already 0, please remove.

Done

https://review.coreboot.org/#/c/30853/2/src/mainboard/purism/librem_skl/Kcon... 
File src/mainboard/purism/librem_skl/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/purism/librem_skl/Kcon... 
PS2, Line 64: 	int "Number of UART port to use for serial log"
> No prompts. The whole point of INTEL_LPSS_UART_FOR_CONSOLE is to […]

Done

https://review.coreboot.org/#/c/30853/2/src/mainboard/purism/librem_skl/Kcon... 
PS2, Line 65: 	default 0
> Oh, default is 0 anyway, so the whole block should be removed.

Done

https://review.coreboot.org/#/c/30853/2/src/mainboard/siemens/mc_apl1/Kconfi... 
File src/mainboard/siemens/mc_apl1/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/siemens/mc_apl1/Kconfi... 
PS2, Line 43: 	int
> I think this conflicts with CB:30836

Removed

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

Patch Set 4: Code-Review+2

(3 comments)

https://review.coreboot.org/#/c/30853/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30853/4//COMMIT_MSG@12 
PS4, Line 12:  
Nit, whitespace at the end of the line

https://review.coreboot.org/#/c/30853/2/src/mainboard/google/reef/Kconfig 
File src/mainboard/google/reef/Kconfig:

https://review.coreboot.org/#/c/30853/2/src/mainboard/google/reef/Kconfig@14 
PS2, Line 14: 	select HAVE_ACPI_TABLES
> Yes, it already select UART2 in Kconfig

Ah, stupid me, I didn't check the existing code, thanks :)

https://review.coreboot.org/#/c/30853/4/src/mainboard/intel/saddlebrook/Kcon... 
File src/mainboard/intel/saddlebrook/Kconfig:

https://review.coreboot.org/#/c/30853/4/src/mainboard/intel/saddlebrook/Kcon... 
PS4, Line 61: 
Nit, accidental removed empty line.

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Lijian Zhao (Code Review)]

Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Hannah Williams, Nico Huber, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30853

to look at the new patch set (#5).

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

soc/mainboard: Update mainboard UART Kconfig

After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao 
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
---
M src/mainboard/google/dragonegg/Kconfig
M src/mainboard/google/eve/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/reef/Kconfig
M src/mainboard/google/sarien/Kconfig
M src/mainboard/intel/apollolake_rvp/Kconfig
M src/mainboard/intel/glkrvp/Kconfig
M src/mainboard/intel/kunimitsu/Kconfig
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
14 files changed, 37 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30853/5

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/#/c/30853/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30853/4//COMMIT_MSG@12 
PS4, Line 12:
> Nit, whitespace at the end of the line

Done

https://review.coreboot.org/#/c/30853/4/src/mainboard/intel/saddlebrook/Kcon... 
File src/mainboard/intel/saddlebrook/Kconfig:

https://review.coreboot.org/#/c/30853/4/src/mainboard/intel/saddlebrook/Kcon... 
PS4, Line 61:
> Nit, accidental removed empty line.

Done

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

Patch Set 5: Code-Review+2

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Bora Guvendik (Code Review)]

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

Patch Set 5: Code-Review+2

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

Patch Set 5: Code-Review+2

Change in ...coreboot[master]: soc/mainboard: Update mainboard UART Kconfig

[Nico Huber (Code Review)]

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30853 )

Change subject: soc/mainboard: Update mainboard UART Kconfig
......................................................................

soc/mainboard: Update mainboard UART Kconfig

After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao 
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: Bora Guvendik 
Reviewed-by: Kyösti Mälkki 
---
M src/mainboard/google/dragonegg/Kconfig
M src/mainboard/google/eve/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/poppy/Kconfig
M src/mainboard/google/reef/Kconfig
M src/mainboard/google/sarien/Kconfig
M src/mainboard/intel/apollolake_rvp/Kconfig
M src/mainboard/intel/glkrvp/Kconfig
M src/mainboard/intel/kunimitsu/Kconfig
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/purism/librem_skl/Kconfig
14 files changed, 37 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Nico Huber: Looks good to me, approved
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig
index 18382d5..39228f4 100644
--- a/src/mainboard/google/dragonegg/Kconfig
+++ b/src/mainboard/google/dragonegg/Kconfig
@@ -8,6 +8,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select SOC_INTEL_ICELAKE

diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index 7c98339..f7fb9c6 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
@@ -75,4 +76,7 @@
    select NHLT_RT5663
    select NHLT_MAX98927

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 26f6f3a..1748d89 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_USES_FSP2_0
    select NO_FADT_8042
@@ -97,4 +98,7 @@
    select NHLT_DMIC_4CH
    select NHLT_MAX98357

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif # BOARD_GOOGLE_BASEBOARD_FIZZ
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 05572df..b75b726 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -13,6 +13,7 @@
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
    select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_LPC_TPM
    select MAINBOARD_HAS_TPM1
@@ -96,4 +97,8 @@
    default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
    default "LARS TEST 5001" if BOARD_GOOGLE_LARS
    default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY
+
+config UART_FOR_CONSOLE
+	int
+	default 2
 endif
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 214a1b6..1fe090f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -9,6 +9,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_SPI_TPM_CR50
    select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 15230dc..a237741 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -13,6 +13,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select SOC_ESPI
    select MAINBOARD_HAS_SPI_TPM_CR50
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index 59abe72..419b10e 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -10,6 +10,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_USES_FSP2_0
    select SOC_INTEL_KABYLAKE
@@ -214,4 +215,7 @@
    select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
    select VBOOT_LID_SWITCH

+config UART_FOR_CONSOLE
+	int
+	default 2
 endif # BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 09b2e61..d2240a8 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -12,6 +12,7 @@
    select EC_GOOGLE_CHROMEEC_LPC
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 5bf4824..ff2f678 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -11,6 +11,7 @@
    select GENERIC_SPD_BIN
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
@@ -82,6 +83,10 @@
    int
    default 8

+config UART_FOR_CONSOLE
+	int
+	default 2
+
 config VARIANT_DIR
    string
    default "arcada" if BOARD_GOOGLE_ARCADA
diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig
index 4afdf0d..ed7d77f 100644
--- a/src/mainboard/intel/apollolake_rvp/Kconfig
+++ b/src/mainboard/intel/apollolake_rvp/Kconfig
@@ -5,6 +5,7 @@
    select SOC_INTEL_APOLLOLAKE
    select BOARD_ROMSIZE_KB_8192
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE

config MAINBOARD_DIR
    string
@@ -18,4 +19,6 @@
    string
    default "Intel"

+config UART_FOR_CONSOLE
+	default 2
 endif
diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig
index 9484559..b3ff2fe 100644
--- a/src/mainboard/intel/glkrvp/Kconfig
+++ b/src/mainboard/intel/glkrvp/Kconfig
@@ -7,6 +7,7 @@
    select DRIVERS_I2C_HID
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_LPC_TPM
    select DRIVERS_GENERIC_MAX98357A
diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig
index e2a6738..f4dd4b1 100644
--- a/src/mainboard/intel/kunimitsu/Kconfig
+++ b/src/mainboard/intel/kunimitsu/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_LPC_TPM
    select SOC_INTEL_SKYLAKE
@@ -72,4 +73,8 @@
    string
    depends on CHROMEOS
    default "KUNIMITSU TEST 8819"
+
+config UART_FOR_CONSOLE
+	int
+	default 2
 endif
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index c8113d2..650d4de 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -24,6 +24,7 @@
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select SERIRQ_CONTINUOUS_MODE
    select SKYLAKE_SOC_PCH_H
    select SOC_INTEL_SKYLAKE
diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig
index d757d1a..12d4bcb 100644
--- a/src/mainboard/purism/librem_skl/Kconfig
+++ b/src/mainboard/purism/librem_skl/Kconfig
@@ -4,6 +4,7 @@
    select BOARD_ROMSIZE_KB_16384
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
    select SOC_INTEL_SKYLAKE
    # Workaround for EC/KBC IRQ1
    select SERIRQ_CONTINUOUS_MODE