Patch merged into coreboot/master: 50214f8 exynos5420: don't assume MPLL for i2c parent clock

the following patch was just integrated into master:
commit 50214f893dd0dd58911bcf3760265c4a58c92d3d
Author: David Hendricks 
Date:   Mon Aug 12 13:24:24 2013 -0700

exynos5420: don't assume MPLL for i2c parent clock

This reads the clock select field for MUX_ACLK_66_SEL in the
    CLK_SRC_TOP1 register in order to obtain the source clock rate
    for I2C peripherals. Before we were always assuming that the source
    was the MPLL.

Unfortunately not all fields in the CLK_SRC_TOPn registers are
    enumerated the same with regard to clock select. So this is just
    a one-off for now.

This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443.

Signed-off-by: David Hendricks

Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f
    Reviewed-on: https://gerrit.chromium.org/gerrit/65611
    Reviewed-by: Ronald G. Minnich 
    Tested-by: David Hendricks 
    Commit-Queue: David Hendricks

See http://review.coreboot.org/4468 for details.

-gerrit