[XS] Change in coreboot[main]: soc/amd/mendocino: Ensure MP2 disable soft fuse bit set properly

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78823?usp=email )

Change subject: soc/amd/mendocino: Ensure MP2 disable soft fuse bit set properly
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soc/amd/mendocino: Ensure MP2 disable soft fuse bit set properly

Commit e728766f4596 ("soc/amd/mendocino: Do not load MP2 Firmware when
in RO") added logic to ensure that the MP2 disable soft fuse bit was set
for the RO section, but failed to check if the bit was already set
otherwise (as it is for non-ChromeOS builds). This caused the bit to
appear twice in the PSP_RO_SOFTFUSE_BITS string, and when the string
was converted to a numeric value, bit (n+1) was set instead of n.

To mitigate this, check that the common PSP_SOFTFUSE_BITS string
doesn't already contain the MP2 disable bit before adding it to the
RO-specific PSP_RO_SOFTFUSE_BITS one.

TEST=build/boot google/skyrim (frostflow). Use a verbose build (V=1)
to verify that the correct soft fuse value is passed to amdfwtool for
RO and RW_A/B for both ChromeOS and non-ChromeOS builds.

Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5
Signed-off-by: Matt DeVillier 
---
M src/soc/amd/mendocino/Makefile.inc
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/78823/1

diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc
index f123487..f99aab3 100644
--- a/src/soc/amd/mendocino/Makefile.inc
+++ b/src/soc/amd/mendocino/Makefile.inc
@@ -236,9 +236,11 @@
 AMDFW_COMMON_ARGS += $(OPT_PSP_LOAD_MP2_FW)
 OPT_PSP_LOAD_MP2_FW =
 else
-# Disable MP2 FW loading in VBOOT RO
+# Disable MP2 FW loading in VBOOT RO if not already disabled
+ifeq ($(findstring 29, $(PSP_SOFTFUSE_BITS)),)
 PSP_RO_SOFTFUSE_BITS += 29
 endif
+endif

$(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
    		$(PSP_VERSTAGE_FILE) \