[XS] Change in coreboot[master]: mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75812?usp=email )

Change subject: mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue
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mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue

Resolve boot issue by tuning RX HS50 and HS200.

BUG=b:265611305
TEST=Reboot test 2500 times pass

Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62
Signed-off-by: Chia-Ling Hou 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75812
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
Reviewed-by: Wisley Chen 
---
M src/mainboard/google/brya/variants/yaviks/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved
  Wisley Chen: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index 65da4fa..7f72f8c 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -59,7 +59,7 @@
    # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
    # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
    # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B223b"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B193b"

# EMMC RX CMD/DATA Delay 2
    # Refer to EDS-Vol2-42.3.12.
@@ -70,7 +70,7 @@
    #         11: Reserved
    # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
    # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004b"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10004"

# EMMC Rx Strobe Delay
    # Refer to EDS-Vol2-42.3.11.