Change in coreboot[master]: [DoNotMerge]soc/intel/cannonlake: Enable Debugging

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29523

Change subject: [DoNotMerge]soc/intel/cannonlake: Enable Debugging
......................................................................

[DoNotMerge]soc/intel/cannonlake: Enable Debugging

Change-Id: I5986007f3f36bc7fdc8e427fa311f98890069cd3
Signed-off-by: Lijian Zhao 
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29523/1

diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index e3b9680..4eaec99 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -8,6 +8,9 @@
    register "gpe0_dw1" = "PMC_GPP_C"
    register "gpe0_dw2" = "PMC_GPP_D"

+    #Debug
+    register "DebugConsent" = DebugConsent_DCI_DBC
+
    # EC host command ranges
    register "gen1_dec" = "0x00040931" # 0x930-0x937
    register "gen2_dec" = "0x00040941" # 0x940-0x947
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 8506214..9c57b12 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -61,6 +61,7 @@
    	m_cfg->PchIshEnable = 0;
    else
    	m_cfg->PchIshEnable = dev->enabled;
+	m_cfg->PchTraceHubMode = 2;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)