[S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Lance Zhao, Subrata Banik, Tarun, Tim Wawrzynczak.

Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email )

Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table
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Patch Set 5:

(3 comments)

File src/acpi/Kconfig:

https://review.coreboot.org/c/coreboot/+/78164/comment/e0b6ad32_fff037a2 :
PS5, Line 95:
> You don't need add an extra line.

Acknowledged

https://review.coreboot.org/c/coreboot/+/78164/comment/74e78b73_747cab24 :
PS5, Line 99: 	 Selected by platforms that slp_s0 freq is varies in different Intel SoC
> Where is the definition of CONFIG_SOC_INTEL_SLP_S0_FREQ ? Why isn't it prefixed with ACPI. […]

Acknowledged

File src/include/acpi/acpi.h:

https://review.coreboot.org/c/coreboot/+/78164/comment/f8df4e84_31b59a9d :
PS4, Line 456: _TSC
> `TSC` is one of the option (0 means TSC), right?

yes, refer https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_I...,
section 2.2.1: value of 0 indicates that counter runs at TSC frequency