Patch set updated for coreboot: 4177ee4 exynos5420: don't assume MPLL for i2c parent clock

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4468

-gerrit

commit 4177ee4e44f2c45c60bf448e8c6daf191a5e8823
Author: David Hendricks 
Date:   Mon Aug 12 13:24:24 2013 -0700

exynos5420: don't assume MPLL for i2c parent clock

This reads the clock select field for MUX_ACLK_66_SEL in the
    CLK_SRC_TOP1 register in order to obtain the source clock rate
    for I2C peripherals. Before we were always assuming that the source
    was the MPLL.

Unfortunately not all fields in the CLK_SRC_TOPn registers are
    enumerated the same with regard to clock select. So this is just
    a one-off for now.

This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443.

Signed-off-by: David Hendricks

Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f
    Reviewed-on: https://gerrit.chromium.org/gerrit/65611
    Reviewed-by: Ronald G. Minnich 
    Tested-by: David Hendricks 
    Commit-Queue: David Hendricks 
---
 src/cpu/samsung/exynos5420/clock.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index 783679a..34d3fb5 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -231,7 +231,23 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
    case PERIPH_ID_I2C8:
    case PERIPH_ID_I2C9:
    case PERIPH_ID_I2C10:
-		sclk = get_pll_clk(MPLL);
+		/*
+		 * I2C block parent clock selection is different from other
+		 * peripherals, so we handle it all here.
+		 * TODO: Add a helper function like with the peripheral clock
+		 * select fields?
+		 */
+		src = (readl(&clk->clk_src_top1) >> 8) & 0x3;
+		if (src == 0x0)
+			src = CPLL;
+		else if (src == 0x1)
+			src = DPLL;
+		else if (src == 0x2)
+			src = MPLL;
+		else
+			return -1;
+
+		sclk = get_pll_clk(src);
    	div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1;
    	return sclk / div;
    default: