Change in coreboot[master]: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En

Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.

BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).

Signed-off-by: John Zhao 
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 11 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41812/1

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index ede5059..f7956c8 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -116,8 +116,17 @@
    m_cfg->TcssXdciEn = config->TcssXdciEn;

/* TCSS DMA */
-	m_cfg->TcssDma0En = config->TcssDma0En;
-	m_cfg->TcssDma1En = config->TcssDma1En;
+	dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
+	if (dev)
+		m_cfg->TcssDma0En = dev->enabled;
+	else
+		m_cfg->TcssDma0En = 0;
+
+	dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
+	if (dev)
+		m_cfg->TcssDma1En = dev->enabled;
+	else
+		m_cfg->TcssDma1En = 0;

/* USB4/TBT */
    dev = pcidev_path_on_root(SA_DEVFN_TBT0);

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

Patch Set 1:

Can you also delete below in chip.h as we don't need to use?

/* TCSS DMA */
uint8_t TcssDma0En;
uint8_t TcssDma1En;

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

Patch Set 1: Code-Review+1

[John Zhao (Code Review)]

Hello Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41812

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En

Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.

BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).

Signed-off-by: John Zhao 
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 11 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41812/2

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

Patch Set 1:
> Patch Set 1:
>
> Can you also delete below in chip.h as we don't need to use?
>
> /* TCSS DMA */
> uint8_t TcssDma0En;
> uint8_t TcssDma1En;

done.

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

Patch Set 2: Code-Review+2

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

Patch Set 2: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En

Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.

BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).

Signed-off-by: John Zhao 
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812
Reviewed-by: Wonkyu Kim 
Reviewed-by: Duncan Laurie 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 11 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 5892829..ed09aaa 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -216,10 +216,6 @@
    uint8_t TcssXhciEn;
    uint8_t TcssXdciEn;

-	/* TCSS DMA */
-	uint8_t TcssDma0En;
-	uint8_t TcssDma1En;
-
    /*
     * IOM Port Config
     * If a port orientation needs to be controlled by the SOC this setting must be
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index ede5059..f7956c8 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -116,8 +116,17 @@
    m_cfg->TcssXdciEn = config->TcssXdciEn;

/* TCSS DMA */
-	m_cfg->TcssDma0En = config->TcssDma0En;
-	m_cfg->TcssDma1En = config->TcssDma1En;
+	dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
+	if (dev)
+		m_cfg->TcssDma0En = dev->enabled;
+	else
+		m_cfg->TcssDma0En = 0;
+
+	dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
+	if (dev)
+		m_cfg->TcssDma1En = dev->enabled;
+	else
+		m_cfg->TcssDma1En = 0;

/* USB4/TBT */
    dev = pcidev_path_on_root(SA_DEVFN_TBT0);

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41812 )

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4442
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4441
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4440
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4439

Please note: This test is under development and might not be accurate at all!