[M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm

[Angel Pons (Code Review)]

Attention is currently required from: Stefan Ott, Arthur Heymans, Alexander Couzens.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69297 )

Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
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Patch Set 18: Code-Review+1

(4 comments)

File src/mainboard/lenovo/t400/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/69297/comment/928c7c8d_ad4384de 
PS18, Line 23: 			# Enable C5, C6
             : 			register "c5" = "1"
             : 			register "c6" = "1"
Where did this go?

File src/mainboard/lenovo/x200/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/69297/comment/8bf14350_e8c20e66 
PS18, Line 23: 			# Enable C5, C6
             : 			register "c5" = "1"
             : 			register "c6" = "1"
Where did this go?

File src/mainboard/roda/rk9/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/69297/comment/9bbc109f_be056391 
PS18, Line 16: 			# Enable C5, C6
             : 			register "c5" = "1"
             : 			register "c6" = "1"
Where did this go?

File src/northbridge/intel/gm45/northbridge.c:

https://review.coreboot.org/c/coreboot/+/69297/comment/93f6dec4_75c997d6 
PS18, Line 264: __pci_0_00_0
> OK, fine with me. I just was wondering since when we have started to use entries from static. […]

`config_of_soc()` would also work.