[XS] Change in coreboot[master]: mb/google/taranza: add USB3 gen2 configuration

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77180?usp=email )

Change subject: mb/google/taranza: add USB3 gen2 configuration
......................................................................

mb/google/taranza: add USB3 gen2 configuration

Taranza Type-C port0 and Type-A port4 will support USB3 gen2,
add gen2 config to enable it.

BUG=b:285811345, b:286002527
TEST=build and verified DUT recognize USB3 gen2 device

Signed-off-by: Sheng-Liang Pan 
Change-Id: I2bbcd123f1c22f7246d1dbea96147681c3f601d0
---
M src/mainboard/google/dedede/variants/taranza/overridetree.cb
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/77180/1

diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
index d563ae1..f432c7a 100644
--- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
@@ -106,7 +106,8 @@
    	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
    }" # Type-A Port A4

-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" #  USB3/1 Type-A Port A4
+	register "usb3_ports[0]" = "USB3_PORT_GEN2_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0
+        register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4
    register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A2
    register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A3