Change in coreboot[master]: Revert "src/soc/intel/cannonlake: Update C-state latency control limits" - coreboot-gerrit

2 Aug 2021


      Attention is currently required from: Bora Guvendik,  Felix Singer, Lijian Zhao, Shaunak Saha, Nico Huber, Martin Roth, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph.
Vaibhav Shankar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
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Patch Set 1:
(1 comment)
Patchset:
PS1: 
The original patch is not a hack. The IRTL values are based out of extensive silicon testing for S0ix on Cannon lake platfrom(initial 10nm).
Please note the current IRTL limits are for 14nm process and does not work on 10nm proess.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6
Gerrit-Change-Number: 56662
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