Patch set updated for coreboot: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17597

-gerrit

commit 9966815b14269e03f8ab5a2a02720bc1fd0bdc07
Author: Arthur Heymans 
Date:   Thu Nov 24 13:23:05 2016 +0100

nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency

This allows to set the backlight PWM frequency and the
    duty cycle in the devicetree instead of using a plain BLC_PWM_CTL
    value.

The previous default PWM frequency was 1006Hz but is now 1000Hz for
    simplicity.

1000Hz is a good default since it typically works well on LED backlit
    displays. A LED backlit display with a too slow PWM causes highly
    annoying flicker, assuming the PWM directly drives the backlight.
    CCFL displays want a lower pwm frequency in the 50-200Hz range.
    Driving a CCFL panel with a too high PWM frequency causes the IC
    to misbehave: unevenly lit backlight and/or high frequency tone.
    Since driving a LED backlit display too slow is worse than driving a
    CCFL backlit display too fast, a fast default is kept.

Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3
    Signed-off-by: Arthur Heymans 
---
 src/northbridge/intel/gm45/chip.h |  2 ++
 src/northbridge/intel/gm45/gma.c  | 35 ++++++++++++++++++++++++++++++++---
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index 836d6bb..2307d53 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -26,6 +26,8 @@ struct northbridge_intel_gm45_config {
    u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
    u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
    struct i915_gpu_controller_info gfx;
+	u32 pwm_freq;
+	u32 duty_cycle;

/*
     * Maximum PCI mmio size in MiB.
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 8938197..054bf05 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -611,6 +611,30 @@ static u8 vga_connected(u8 *mmio)
    return 1;
 }

+/*
+ * In principle the display core clock is
+ * (PP_DIVISOR[31:16] + 1) * 2 / 100 * MHz.
+ * Since PP_DIVISOR[31:16] is not touched it will be at its default value
+ * of 0x270f, hence the default display core clock is 200MHz.
+ * This is done in order to avoid potential overflows.
+ */
+
+#define DEFAULT_CORE_CLOCK 200000000
+
+static u32 freq_to_blc_pwm_ctl(u16 pwm_freq, u16 duty_perc)
+{
+	u32 blc_mod;
+
+	blc_mod = DEFAULT_CORE_CLOCK / (128 * pwm_freq);
+
+	if (duty_perc <= 100)
+		return (blc_mod << 16) | (blc_mod * duty_perc / 100);
+	else
+		return (blc_mod << 16) | blc_mod;
+}
+
+#define DEFAULT_PWM_FREQ 1000
+
 static void gma_pm_init_post_vbios(struct device *const dev)
 {
    const struct northbridge_intel_gm45_config *const conf = dev->chip_info;
@@ -643,10 +667,15 @@ static void gma_pm_init_post_vbios(struct device *const dev)

/* Enable Backlight  */
    gtt_write(BLC_PWM_CTL2, (1 << 31));
-	if (conf->gfx.backlight == 0)
-		gtt_write(BLC_PWM_CTL, 0x06100610);
+	reg32 = 100;
+	if (conf->duty_cycle != 0)
+		reg32 = conf->duty_cycle;
+	if (conf->pwm_freq == 0)
+		gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(DEFAULT_PWM_FREQ,
+								reg32));
    else
-		gtt_write(BLC_PWM_CTL, conf->gfx.backlight);
+		gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(conf->pwm_freq,
+								reg32));
 }

static void gma_func0_init(struct device *dev)