hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49006 )
Change subject: WIP: soc/mediatek/mt8192: add mt6359p efuse setting ......................................................................
WIP: soc/mediatek/mt8192: add mt6359p efuse setting
Some efuse settings would not be applied automatically, so we need set the settings manually.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: Ideb862c3cb0f1fee183804aed74fcf141bf1f5df --- M src/soc/mediatek/mt8192/include/soc/mt6359p.h M src/soc/mediatek/mt8192/mt6359p.c 2 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/49006/1
diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h index b90e0f5..1d01d71 100644 --- a/src/soc/mediatek/mt8192/include/soc/mt6359p.h +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -8,8 +8,15 @@ enum { PMIC_HWCID = 0x0008, PMIC_SWCID = 0x000a, + PMIC_TOP_CKPDN_CON0 = 0x010c, + PMIC_TOP_CKHWEN_CON0 = 0x012a, PMIC_TOP_RST_MISC_SET = 0x014c, PMIC_TOP_RST_MISC_CLR = 0x014e, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_PWRHOLD = 0x0a08, PMIC_VGPU11_DBG0 = 0x15a6, PMIC_VGPU11_ELR0 = 0x15b4, @@ -30,6 +37,13 @@ unsigned char shift; };
+struct pmic_efuse { + unsigned short efuse_bit; + unsigned short addr; + unsigned short mask; + unsigned char shift; +}; + enum { MT6359P_GPU11 = 0, MT6359P_SRAM_PROC1, @@ -40,6 +54,8 @@ #define VM18_VOL_REG_SHIFT 8 #define VM18_VOL_OFFSET 600
+#define EFUSE_WAIT_US 5000 +#define EFUSE_BUSY 1 void mt6359p_init(void); void mt6359p_romstage_init(void); void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv); diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index 18513a0..908ce30 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -5,6 +5,7 @@ #include <delay.h> #include <soc/pmif.h> #include <soc/mt6359p.h> +#include <timer.h>
static const struct pmic_setting key_protect_setting[] = { {0x3A8, 0x9CA6, 0xFFFF, 0}, @@ -287,6 +288,32 @@ {0x1d14, 0x1, 0x1, 0x2}, };
+static const struct pmic_efuse efuse_setting[] = { + {79, 0xa0e, 0x1, 0xf}, + {886, 0x198c, 0xf, 0x8}, + {890, 0x198e, 0xf, 0x0}, + {902, 0x1998, 0xf, 0x8}, + {906, 0x1998, 0xf, 0xc}, + {918, 0x19a2, 0xf, 0x8}, + {922, 0x19a2, 0xf, 0xc}, + {1014, 0x19ae, 0xf, 0x7}, + {1018, 0x19ae, 0xf, 0xb}, + {1158, 0x1a0a, 0xf, 0x7}, + {1162, 0x1a0a, 0xf, 0xb}, + {1206, 0x1a16, 0xf, 0x7}, + {1210, 0x1a16, 0xf, 0xb}, + {1254, 0x1a22, 0xf, 0x7}, + {1258, 0x1a22, 0xf, 0xb}, + {1304, 0x1a2c, 0x7, 0x4}, + {1307, 0x1a32, 0x7, 0x8}, + {1336, 0x1a34, 0x7, 0x4}, + {1339, 0x1a3a, 0x7, 0x8}, + {1683, 0x79c, 0xf, 0x4}, + {1688, 0xc8a, 0x1, 0x3}, + {1689, 0xc88, 0x1, 0x3}, + {1690, 0xc88, 0x7, 0x0}, +}; + static struct pmif *pmif_arb = NULL; static void mt6359p_write(u32 reg, u32 data) { @@ -318,6 +345,52 @@ mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0); }
+static int check_idle(u32 addr, u32 mask) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, EFUSE_WAIT_US); + do { + reg_rdata = mt6359p_read_field(addr, mask, 0); + if (stopwatch_expired(&sw)) + return -1; + } while (reg_rdata); + + return 0; +} + +static u32 pmic_read_efuse(u32 efuse_bit, u32 mask) +{ + u32 efuse_data = 0; + int ret, index, shift; + + index = efuse_bit / 16; + shift = efuse_bit % 16; + mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 0, 0x1, 2); + mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 0, 0x1, 4); + mt6359p_write_field(PMIC_OTP_CON11, 1, 0x1, 0); + mt6359p_write_field(PMIC_OTP_CON0, index * 2, 0xFF, 0); + if (mt6359p_read_field(PMIC_OTP_CON8, 1, 0)) + mt6359p_write_field(PMIC_OTP_CON8, 0, 1, 0); + else + mt6359p_write_field(PMIC_OTP_CON8, 1, 1, 0); + + udelay(300); + ret = check_idle(PMIC_OTP_CON13, EFUSE_BUSY); + if (ret) + die("ERROR: Read efuse data timeout"); + udelay(100); + + efuse_data = mt6359p_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + + mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 1, 0x1, 2); + mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 1, 0x1, 4); + + efuse_data = (efuse_data >> shift) & mask; + return efuse_data; +} + static void pmic_protect_key_set(bool lock) { if (lock) { @@ -343,6 +416,17 @@ lp_setting[i].mask, lp_setting[i].shift); }
+static void pmic_efuse_setting(void) +{ + u32 efuse_data; + + for (int i = 0; i < ARRAY_SIZE(efuse_setting); i++) { + efuse_data = pmic_read_efuse(efuse_setting[i].efuse_bit, efuse_setting[i].mask); + mt6359p_write_field(efuse_setting[i].addr, efuse_data, + efuse_setting[i].mask, efuse_setting[i].shift); + } +} + static void pmic_wk_vs2_voter_setting(void) { /* @@ -463,6 +547,7 @@ pmic_protect_key_set(false); pmic_init_setting(); pmic_lp_setting(); + pmic_efuse_setting(); pmic_protect_key_set(true); pmic_wk_vs2_voter_setting(); }