[S] Change in coreboot[main]: mb/google/brya/var/trulo: Update PL1 values as per silicon TDP

[Vidya Gopalakrishnan (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, V Sowmya, Vidya Gopalakrishnan, Vinay Kumar.

Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, V Sowmya, Vinay Kumar, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85184?usp=email

to look at the new patch set (#4).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: mb/google/brya/var/trulo: Update PL1 values as per silicon TDP
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mb/google/brya/var/trulo: Update PL1 values as per silicon TDP

Update the RAPL PL1 limit and MMIO PL1 max values as per silicon TDP.

BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.

Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan 
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 4 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85184/4