Change in coreboot[master]: soc/amd: Move DRAM structure loading to agesawrapper

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21857

Change subject: soc/amd: Move DRAM structure loading to agesawrapper
......................................................................

soc/amd: Move DRAM structure loading to agesawrapper

Let the generic AGESA wrapper load the PlatformMemoryConfiguration
pointer with a mainboard default.  For more complex configurations
the mainboard may still override any structure(s) in the list.

Change-Id: I2bb6e188f17644c57099c0696bae613e5dd8d34f
Signed-off-by: Marshall Dawson 
---
M src/mainboard/amd/gardenia/OemCustomize.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/soc/amd/common/agesawrapper.c
3 files changed, 8 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/21857/1

diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index b8b3fea..560ece8 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -23,7 +23,7 @@
 #error "Too many DIMM sockets defined for the mainboard"
 #endif

-static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+const PSO_ENTRY mainboard_dram_defaults[] = {
    DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
    NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS),
    NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
@@ -36,9 +36,3 @@
    			0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
    PSO_END
 };
-
-void OemPostParams(AMD_POST_PARAMS *PostParams)
-{
-	PostParams->MemConfig.PlatformMemoryConfiguration =
-				(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
-}
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 878e2b9..50d504d 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -23,7 +23,7 @@
 #error "Too many DIMM sockets defined for the mainboard"
 #endif

-static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+const PSO_ENTRY mainboard_dram_defaults[] = {
    DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
    NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS),
    NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
@@ -39,8 +39,6 @@

void OemPostParams(AMD_POST_PARAMS *PostParams)
 {
-	PostParams->MemConfig.PlatformMemoryConfiguration =
-				(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
    /* disable memory clear for pstore memory storage and boot time */
    PostParams->MemConfig.EnableMemClr = FALSE;
 }
diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c
index 93f7eb4..95c20d7 100644
--- a/src/soc/amd/common/agesawrapper.c
+++ b/src/soc/amd/common/agesawrapper.c
@@ -24,11 +24,14 @@
 #include <FchPlatform.h>
 #include <heapManager.h>
 #include <agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
 #include <BiosCallOuts.h>

void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}

#define FILECODE UNASSIGNED_FILE_FILECODE
+
+extern const PSO_ENTRY mainboard_dram_defaults[];

#ifndef __PRE_RAM__
 /* ACPI table pointers returned by AmdInitLate */
@@ -156,7 +159,9 @@
    				UMA_AUTO : UMA_NONE;
    }
    PostParams->MemConfig.BottomIo = (UINT16)
-					 (CONFIG_BOTTOMIO_POSITION >> 24);
+					(CONFIG_BOTTOMIO_POSITION >> 24);
+	PostParams->MemConfig.PlatformMemoryConfiguration =
+					(PSO_ENTRY *)mainboard_dram_defaults;

OemPostParams(PostParams);