frank vibrans has uploaded this change for review. ( https://review.coreboot.org/21564
Change subject: soc/amd/stoneyridge: PSP SMM implementation (WIP) ......................................................................
soc/amd/stoneyridge: PSP SMM implementation (WIP)
Add end of post bios to psp smm mailbox path. Add psp to bios smm mailbox path. Test code included - will be removed later.
Change-Id: Id747289b62e3d450a901401eafa9ac243e6aa25d Signed-off-by: Frank Vibrans frank.vibrans@scarletltd.com
soc/amd/stoneyridge: BIOS-PSP SMM interface framework
Add end-of-post BIOS-to-PSP smm mailbox path. Add PSP-to-BIOS smm mailbox path. Test code removed. SPI access code not yet in place.
Change-Id: I88d45b73263369917b67a2e586f44e331bb7028b Signed-off-by: Frank Vibrans frank.vibrans@scarletltd.com --- M src/soc/amd/common/block/include/amdblocks/psp.h A src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h A src/soc/amd/common/block/include/amdblocks/psp_init.h A src/soc/amd/common/block/include/amdblocks/psp_smm.h M src/soc/amd/common/block/psp/Makefile.inc A src/soc/amd/common/block/psp/p2cmbox.c M src/soc/amd/common/block/psp/psp.c A src/soc/amd/common/block/psp/psp_get_mbox.c A src/soc/amd/common/block/psp/psp_init.c A src/soc/amd/common/block/psp/psp_init_smm.c A src/soc/amd/common/block/psp/psp_smm_get_mbox.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smihandler.c 14 files changed, 737 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21564/1
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 42b9fb7..36f743c 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,8 +18,24 @@
#include <stdint.h> #include <compiler.h> -#include <Porting.h> -#include <Proc/Psp/PspBaseLib/PspBaseLib.h> + +/* This block MUST match the file + * src/vendorcode/amd/pi/00670f00/Proc/Psp/PspBaseLib/PspBaseLib.h */ +#define PSP_PCI_SEG 0x00 ///< PSP Seg address +#define PSP_PCI_BUS 0x00 ///< PSP Bus address +#define PSP_PCI_DEV 0x08 ///< PSP Device address +#define PSP_PCI_FN 0x00 ///< PSP Fn address +#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8)) +#define GET_PSP_PCI_ADDR(Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset) + +#define PSP_PCI_DEVID_REG 0x00 ///< DevId +#define PSP_PCI_CMD_REG 0x04 ///< CmdReg +#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1 +#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3 +#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1 +#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr +#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability +/* End of PspBaseLib.h matching block */
/* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 @@ -70,6 +86,37 @@ struct mbox_buffer_header header; } __attribute__((packed,aligned(32)));
+/* Definitions for MboxBiosCmdSmmInfo buffer - command 0x2 */ +#define PSP_SMMINFO_TYPE_IO 0 +#define PSP_SMMINFO_TYPE_MMIO 1 +#define PSP_SMMINFO_TYPE_PCI 2 + +#define PSP_SMMINFO_WIDTH_BYTE 0 +#define PSP_SMMINFO_WIDTH_WORD 1 +#define PSP_SMMINFO_WIDTH_DWORD 2 +#define PSP_SMMINFO_WIDTH_QWORD 3 + +struct smm_trigger_info { + u64 address; + u32 address_type; + u32 value_width; + u32 value_and_mask; + u32 value_or_mask; +} __attribute__((packed,aligned(32))); + +struct smm_req_buffer { + u64 smm_base; + u64 smm_length; + u64 psp_smm_data_base; + u64 psp_smm_data_length; + struct smm_trigger_info smm_trig_info; +} __attribute__((packed,aligned(32))); + +struct mbox_smm_info_buffer { + struct mbox_buffer_header header; + struct smm_req_buffer req; +} __attribute__((packed,aligned(32))); + /* send_psp_command() error codes */ #define PSPSTS_SUCCESS 0 #define PSPSTS_NOBASE 1 @@ -93,5 +140,7 @@
/* BIOS-to-PSP functions return 0 if successful, else negative value */ int psp_notify_dram(void); +int psp_notify_smm_info(uintptr_t base, u64 length, uintptr_t psp_data_base, + u64 psp_data_length, struct smm_trigger_info *smm_trig_info);
#endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h b/src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h new file mode 100644 index 0000000..1dc885b --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMD_PSP_GET_MBOX_H +#define AMD_PSP_GET_MBOX_H + +struct psp_mbox *get_mbox_address(void); +void PSPProgBar3Msr(void); + +#endif /* AMD_PSP_GET_MBOX_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp_init.h b/src/soc/amd/common/block/include/amdblocks/psp_init.h new file mode 100644 index 0000000..3612cd5 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/psp_init.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_PSP_INIT_H__ +#define __AMD_PSP_INIT_H__ + +/* Trap 0xfed80e00 memory read, no override */ +#define MEMTRAP0_CONFIG 0xfed80e00 + +void psp_initialize(void); +//void enable_smi_generation(void); +void disable_smi_generation(void); +void clear_smi_status(void); + +#endif /* __AMD_PSP_INIT_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp_smm.h b/src/soc/amd/common/block/include/amdblocks/psp_smm.h new file mode 100644 index 0000000..1a96c10 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/psp_smm.h @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_PSP_SMM_H__ +#define __AMD_PSP_SMM_H__ + +#include <stdint.h> + +/* PSP Directory Entry Type Encodings */ +#define TYPE_AMD_PUBKEY 0x00 +#define TYPE_BOOT_LOAD_FW 0x01 +#define TYPE_SECURE_OS_FW 0x02 +#define TYPE_REC_BOOT_LDR 0x03 +#define TYPE_NON_VOL_DATA 0x04 +#define TYPE_SIGNED_OEM_BIOS_PUBKEY 0x05 +#define TYPE_BIOS_RTM_VOLUME 0x06 +#define TYPE_BIOS_RTM_OEMSIG 0x07 +#define TYPE_SMU_OFFCHIP_FW 0x08 +#define TYPE_AMD_SEC_DEBKEY 0x09 +#define TYPE_SIGNED_SEC_OS_PUBKEY 0x0a +#define TYPE_SOFT_FUSE_CHAIN 0x0b +#define TYPE_LOADED_TPM96_TR_BINARY 0x0c +#define TYPE_SIGNED_TR_PUBKEY 0x0d + +#define TYPE_S3_MEM_BOOT_LDR 0x10 +#define TYPE_SMU_OFFCHIP_FW2 0x12 +#define TYPE_LOADED_TPM122_TR_BINARY 0x14 +#define TYPE_S3_DATA_BLOB_ENTRY_PTR 0x1a +#define TYPE_SW_CONFIG_DATA_BLK 0x5f + +#define TYPE_OEM_TA 0x80 +#define TYPE_SIGNED_OEM_TA_PUBKEY 0x81 + +#define PSP_DATA_BLK_SIZE (8 * 1024) + 32 + +struct psp_embedded_fw { + u32 signature; + u32 reserved1; + u32 imc_fw_entry; + u32 xhci_fw_entry; + u32 psp_dir_table; + u32 new_psp_dir_table; + u32 reserved2[10]; + u8 spi_mode; + u8 spi_read_spd; + u16 reserved3; +} __attribute__ ((packed)); + +struct p2cmbox_dir_tbl_hdr { + u32 cookie; + u32 chksum; + u32 num_entries; + u32 reserved; +} __attribute__ ((packed)); + +struct p2cmbox_dir_tbl_entry { + u32 type; + u32 size; + u64 loc_val; +} __attribute__ ((packed)); + +/* PSP to BIOS commands */ +#define SPI_GET_ATTRIBUTE 0x81 +#define SPI_SET_ATTRIBUTE 0x82 /* Not currently supported */ +#define SPI_GET_BLOCKSIZE 0x83 +#define SPI_READ_FW_VOLUME 0x84 +#define SPI_READ_WR_VOLUME 0x85 +#define SPI_ERASE_FW_VOLUME 0x86 + +struct psp_smm_mailbox { + u8 buffer[PSP_DATA_BLK_SIZE]; +} __attribute__ ((packed,aligned (32))); + +struct spi_info_req { + u64 lba; + u64 blocksize; + u64 number_of_blocks; +} __attribute__ ((packed)); + +struct spi_rw_fw_vol { + u64 lba; + u64 offset; + u64 number_of_bytes; + u8 *buffer; +} __attribute__ ((packed)); + +struct spi_erase_fw_vol { + u64 lba; + u64 number_of_blocks; +} __attribute__ ((packed)); + +#define PSP_CMD_STATUS_CMD_READY (1 << 31) +#define PSP_CMD_STATUS_CHKSUM_ENABLE (1 << 8) +struct psp_smi_mbox_status { + u32 checksum_value:8; + u32 checksum_enable:1; + u32 reserved:22; + u32 command_ready:1; +} __attribute__ ((packed)); + +struct psp_smi_mbox_buffer_header { + u32 total_size; + u32 status; +} __attribute__ ((packed)); + +struct psp_smm_mbox { + u32 command; + struct psp_smi_mbox_status status; + u8 buffer[]; +} __attribute__ ((packed)); + +/* command specific command/response buffer layouts */ +/* SPI_GET_ATTRIBUTE (0x81) and SPI_SET_ATTRIBUTE (0x82) */ +struct spi_attrib { + struct psp_smi_mbox_buffer_header header; + u64 attribute; +} __attribute__ ((packed)); + +/* SPI_GET_BLOCKSIZE (0x83) */ +struct spi_blocksize { + struct psp_smi_mbox_buffer_header header; + struct spi_info_req block_data; +} __attribute__ ((packed)); + +/* SPI_READ_FW_VOLUME (0x84) and SPI_WRITE_FW_VOLUME (0x85) */ +struct spi_fw_vol { + struct psp_smi_mbox_buffer_header header; + struct spi_rw_fw_vol data; +} __attribute__ ((packed)); + +/* SPI_ERASE_FW_VOLUME (0x86) */ +struct spi_erase_req { + struct psp_smi_mbox_buffer_header header; + struct spi_erase_fw_vol block_data; +} __attribute__ ((packed)); + +extern struct psp_smm_mailbox psp_smm_mbox; + +void psp_p2cmbox_init(u32 status); +void psp_smm_init(u32 status); +void psp_p2cmbox_event(u32 status); +uint8_t test_checksum(u8 *start, u32 len); + +#endif /* __AMD_PSP_SMM_H__ */ diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index eebba16..9d314a0 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -1,2 +1,10 @@ romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_get_mbox.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_get_mbox.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_init.c + +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_init_smm.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_smm_get_mbox.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += p2cmbox.c diff --git a/src/soc/amd/common/block/psp/p2cmbox.c b/src/soc/amd/common/block/psp/p2cmbox.c new file mode 100644 index 0000000..38a2574 --- /dev/null +++ b/src/soc/amd/common/block/psp/p2cmbox.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/amdfam15.h> +#include <amdblocks/psp.h> +#include <amdblocks/psp_smm.h> +#include <soc/smi.h> + +struct psp_smm_mailbox psp_smm_mbox; + +uint8_t test_checksum(uint8_t *start, uint32_t len) +{ + uint8_t test_sum = 0; + uint32_t i; + + for (i=0; i<len; i++) { + test_sum += *(uint8_t *)(start + i); + }; + + return test_sum; +} + +void psp_p2cmbox_event(uint32_t status) +{ + /* Check for supported SMI */ + if (!(status & SMISTAT4_FAKESMI_0)) + return; + + uintptr_t psp_data_base = (uintptr_t)&psp_smm_mbox; + + /* Check if a command is ready */ + uint32_t cmd_status = *(uint32_t *)(psp_data_base + 4); + if (!(cmd_status & PSP_CMD_STATUS_CMD_READY)) + return; + + /* Test checksum if necessary */ + if (cmd_status & PSP_CMD_STATUS_CHKSUM_ENABLE) { + uint32_t length = *(uint32_t *)(psp_data_base + 8); + if (test_checksum((uint8_t *)psp_data_base, length)) + return; + }; + + /* */ + uint32_t psp_cmd = *(uint32_t *)psp_data_base; + switch (psp_cmd) { + case SPI_GET_ATTRIBUTE: + break; + /* case SPI_SET_ATTRIBUTE Not currently supported */ + /* break; */ + case SPI_GET_BLOCKSIZE: + break; + case SPI_READ_FW_VOLUME: + break; + case SPI_READ_WR_VOLUME: + break; + case SPI_ERASE_FW_VOLUME: + break; + default: + return; + } +} diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index d61a914..3b6ef5e 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -20,6 +20,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <amdblocks/psp.h> +#include <amdblocks/psp_get_mbox.h>
static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; static const char *psp_status_halted = "error: PSP in halted state"; @@ -47,24 +48,6 @@ default: return psp_status_noerror; } -} - -static struct psp_mbox *get_mbox_address(void) -{ - UINT32 base; /* UINT32 for compatibility with PspBaseLib */ - BOOLEAN bar3_status; - uintptr_t baseptr; - - bar3_status = GetPspBar3Addr(&base); - if (!bar3_status) { - PspBarInitEarly(); - bar3_status = GetPspBar3Addr(&base); - } - if (!bar3_status) - return NULL; - - baseptr = base; - return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); }
static u32 rd_mbox_sts(struct psp_mbox *mbox) @@ -201,3 +184,32 @@
return cmd_status; } + +/* + * Inform the PSP of the systems System Management Mode settings. + */ +int psp_notify_smm_info(uintptr_t base, u64 length, uintptr_t psp_data_base, + u64 psp_data_length, struct smm_trigger_info *smm_trig_info) +{ + struct mbox_smm_info_buffer buffer; + int cmd_status; + + printk(BIOS_DEBUG, "PSP: Notify SMM info... "); + + buffer.header.size = sizeof(struct mbox_smm_info_buffer); + buffer.header.status = 0; + buffer.req.smm_base = base; + buffer.req.smm_length = length; + buffer.req.psp_smm_data_base = psp_data_base; + buffer.req.psp_smm_data_length = psp_data_length; + buffer.req.smm_trig_info = *smm_trig_info; + + cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); + + if (cmd_status) + printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); + else + printk(BIOS_DEBUG, "OK\n"); + + return cmd_status; +} diff --git a/src/soc/amd/common/block/psp/psp_get_mbox.c b/src/soc/amd/common/block/psp/psp_get_mbox.c new file mode 100644 index 0000000..19812da --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_get_mbox.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <Porting.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <Proc/Psp/PspBaseLib/PspBaseLib.h> +#include <amdblocks/psp.h> +#include <amdblocks/psp_get_mbox.h> + +struct psp_mbox *get_mbox_address(void) +{ + UINT32 base; /* UINT32 for compatibility with PspBaseLib */ + BOOLEAN bar3_status; + uintptr_t baseptr; + + bar3_status = GetPspBar3Addr(&base); + if (!bar3_status) { + PspBarInitEarly(); + bar3_status = GetPspBar3Addr(&base); + } + if (!bar3_status) + return NULL; + + baseptr = base; + return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); +} + +void PSPProgBar3Msr(void) +{ + UINT32 Bar3Addr; + UINT64 Tmp64; + + /* Get Bar3 Addr */ + Bar3Addr = PspLibPciReadPspConfig(0x20); + Tmp64 = Bar3Addr; + printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); + LibAmdMsrWrite(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); + /* LibAmdMsrRead(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); */ +} diff --git a/src/soc/amd/common/block/psp/psp_init.c b/src/soc/amd/common/block/psp/psp_init.c new file mode 100644 index 0000000..dea7717 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_init.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <soc/smi.h> +#include <amdblocks/psp.h> +#include <amdblocks/psp_init.h> +#include <amdblocks/psp_get_mbox.h> + +/** Clear the EOS bit and disable SMI generation from southbridge */ +void disable_smi_generation(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_SMIENB; /* Disable SMI generation */ + reg &= ~SMITRG0_EOS; /* Clear EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +/** Arbitrarily clear all SMI status by reading each status + register and writing the read data back into it. +*/ +void clear_smi_status(void) +{ + uint32_t reg = smi_read32(SMI_REG_GPESTAT); + smi_write32(SMI_REG_GPESTAT, reg); + + reg = smi_read32(SMI_REG_SMISTAT0); + smi_write32(SMI_REG_SMISTAT0, reg); + + reg = smi_read32(SMI_REG_SMISTAT1); + smi_write32(SMI_REG_SMISTAT1, reg); + + reg = smi_read32(SMI_REG_SMISTAT2); + smi_write32(SMI_REG_SMISTAT2, reg); + + reg = smi_read32(SMI_REG_SMISTAT4); + smi_write32(SMI_REG_SMISTAT4, reg); +} + +void psp_initialize(void) +{ + uint32_t reg; + uint32_t *mem_ptr = (uint32_t *)MEMTRAP0_CONFIG; + + /* Required setup */ + PSPProgBar3Msr(); + + disable_smi_generation(); + + /* Set up for trap on read because it is non-destructive */ + smi_write32(SMI_REG_MEM_TRAP0, MEMTRAP0_CONFIG); + + /* Enable the memory read trap */ + reg = smi_read32(SMI_REG_SMICTRL9); + reg |= SMICTRL9_MTRAP_EN; + smi_write32(SMI_REG_SMICTRL9, reg); + + clear_smi_status(); + + enable_smi_generation(); + + /* Trigger SMI that starts PSP SMM initialization*/ + reg = *mem_ptr; +} diff --git a/src/soc/amd/common/block/psp/psp_init_smm.c b/src/soc/amd/common/block/psp/psp_init_smm.c new file mode 100644 index 0000000..c69d071 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_init_smm.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/amdfam15.h> +#include <amdblocks/psp.h> +#include <amdblocks/psp_smm.h> +#include <soc/smi.h> + +void psp_p2cmbox_init(uint32_t status) +{ + struct smm_trigger_info trig_info; + + /* Have FakeSMI0 generate an SMI with status routed to SmiStatus4 */ + uint32_t reg = smi_read32(SMI_REG_SMICTRL8); + reg |= SMICTRL8_FAKE0_SMI_EN; + smi_write32(SMI_REG_SMICTRL8, reg); + + /* Determine MBoxBiosCmdSmmInfo message parameters */ + /* SMI trigger information */ + trig_info.address = (uintptr_t)(SMI_BASE + SMI_REG_SMITRIG0); + trig_info.address_type = PSP_SMMINFO_TYPE_MMIO; + trig_info.value_width = PSP_SMMINFO_WIDTH_WORD; + trig_info.value_and_mask = ~SMITRG0_FAKE0; + trig_info.value_or_mask = SMITRG0_FAKE0; + + /* TSEG information */ + msr_t msr = rdmsr(MSR_TSEG_BASE); + uintptr_t tseg_base = ((uint64_t)(msr.hi) << 32) | (uint64_t)(msr.lo); + msr = rdmsr(MSR_SMM_MASK); + /* The size mask extends from bit 17 to bit 47, but it is not + likely we will see a TSEG greater than 2GB, so we will cheat + in our math and ignore mask bits 32-47. */ + uint64_t tseg_length = (uint64_t)(~(msr.lo)) + (uint64_t)1; + + /* PSP SMM mailbox information */ + uintptr_t psp_data_base = (uintptr_t)&psp_smm_mbox; + uint64_t psp_data_length = sizeof(psp_smm_mbox); + + /* Now send the MBoxBiosCmdSmmInfo command to the PSP */ + psp_notify_smm_info(tseg_base, tseg_length, psp_data_base, + psp_data_length, (struct smm_trigger_info *)&trig_info); +} + +void psp_smm_init(uint32_t status) +{ + /* Disable memory read trap that got us here */ + uint32_t reg = smi_read32(SMI_REG_SMICTRL9); + reg &= ~SMICTRL9_MTRAP_MASK; + smi_write32(SMI_REG_SMICTRL9, reg); + + /* Clear the memory trap address */ + smi_write32(SMI_REG_MEM_TRAP0, (uint32_t)0); + + psp_p2cmbox_init(status); +} diff --git a/src/soc/amd/common/block/psp/psp_smm_get_mbox.c b/src/soc/amd/common/block/psp/psp_smm_get_mbox.c new file mode 100644 index 0000000..6ec0f12 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp_smm_get_mbox.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <amdblocks/psp.h> +#include <amdblocks/psp_get_mbox.h> + +struct psp_mbox psp_c2p_smm_mbox; + +struct psp_mbox *get_mbox_address(void) +{ + return (struct psp_mbox *)&psp_c2p_smm_mbox; +} + +void PSPProgBar3Msr(void) +{ + printk(BIOS_DEBUG, "SMM stub - PSPProgBar3Msr\n"); +} diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index fe4ab9f..9f1ca9b 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -28,6 +28,7 @@ #include <soc/southbridge.h> #include <soc/smi.h> #include <console/console.h> +#include <amdblocks/psp_init.h> #include <cpu/amd/amdfam15.h> #include <smp/node.h>
@@ -109,9 +110,15 @@ .post_mp_init = enable_smi_generation, };
+void __attribute__((weak)) psp_initialize(void) { /* no-op */ } + void stoney_init_cpus(struct device *dev) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) { printk(BIOS_ERR, "MP initialization failure.\n"); + return; + } + + psp_initialize(); } diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 46004c9..6f7cadb 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -16,11 +16,107 @@ */ #define SMI_BASE 0xfed80200
+#define SMI_REG_GPESTAT 0x00 /* GPE event status */ +#define SMI_REG_GPE_EVT_EN 0x04 /* GPE event enable */ + +#define SMI_REG_SCI_TRIGGER 0x08 +#define SMI_REG_SCI_LEVEL 0x0c +#define SMI_REG_SCI_STATUS 0x10 +#define SMI_REG_SCI_ENABLE 0x14 +#define SMI_REG_SW_SCI_ENABLE 0x18 +#define SMI_REG_SW_SCI_DATA 0x1c +#define SMI_REG_SCI_SLP_DISABLE 0x20 + +#define SMI_REG_CAPTURED_DATA 0x30 +#define SMI_REG_CAPTURED_VALID 0x34 +#define SMI_REG_EPBIF_AER_STPS 0x38 +#define SMI_REG_DATA_ERR_STS 0x3c + +#define SMI_REG_SCI_MAP0 0x40 +#define SMI_REG_SCI_MAP1 0x44 +#define SMI_REG_SCI_MAP2 0x48 +#define SMI_REG_SCI_MAP3 0x4c +#define SMI_REG_SCI_MAP4 0x50 +#define SMI_REG_SCI_MAP5 0x54 +#define SMI_REG_SCI_MAP6 0x58 +#define SMI_REG_SCI_MAP7 0x5c +#define SMI_REG_SCI_MAP8 0x60 +#define SMI_REG_SCI_MAP9 0x64 +#define SMI_REG_SCI_MAP10 0x68 +#define SMI_REG_SCI_MAP11 0x6c +#define SMI_REG_SCI_MAP12 0x70 +#define SMI_REG_SCI_MAP13 0x74 +#define SMI_REG_SCI_MAP14 0x78 +#define SMI_REG_SCI_MAP15 0x7c + +#define SMI_REG_SMISTAT0 0x80 +#define SMI_REG_SMISTAT1 0x84 +#define SMISTAT1_FAKESMI_0 (1 << 1) +#define SMISTAT1_FAKESMI_1 (1 << 2) +#define SMISTAT1_FAKESMI_2 (1 << 3) +#define SMISTAT1_FAKESMI_EVTS (0b111 << 1) +#define SMISTAT1_FAKE_SMI_EVTS (SMISTAT1_FAKESMI_0 | SMISTAT1_FAKESMI_1 | SMISTAT1_FAKESMI_2) +#define SMISTAT1_ECGE0_EVTS (1 << 8) +#define SMISTAT1_TWARN_EVTS (1 << 16)) +#define SMISTAT1_PWRBTN_EVTS (1 << 19) +#define SMISTAT1_PROCHOT_EVTS (1 << 20) +#define SMI_REG_SMISTAT2 0x88 +#define SMISTAT2_SLPTYP_EVTS (1 << 1) +#define SMISTAT2_PWRBTN_EVTS (1 << 10) +#define SMISTAT2_ACPI_CMD_EVTS (1 << 11) +#define SMISTAT2_ECSMI0_EVTS (1 << 15) +#define SMISTAT2_PROCHOT_EVTS (1 << 19) +#define SMI_REG_SMISTAT3 0x8c +#define SMI_REG_SMISTAT4 0x90 +#define SMISTAT4_FAKESMI_EVTS (0b111 << 10) +#define SMISTAT4_FAKESMI_0 (1 << 10) +#define SMISTAT4_FAKESMI_1 (1 << 11) +#define SMISTAT4_FAKESMI_2 (1 << 12) +#define SMISTAT4_MEMTRAP_EVT (1 << 24) + +#define SMI_REG_SMI_TIMERT 0x94 + #define SMI_REG_SMITRIG0 0x98 -#define SMITRG0_EOS (1 << 28) #define SMITRG0_SMIENB (1 << 31) +#define SMITRG0_EOS (1 << 28) +#define SMITRG0_FAKE2 (1 << 27) +#define SMITRG0_FAKE1 (1 << 26) +#define SMITRG0_FAKE0 (1 << 25) + +#define SMI_REG_SMITRIG1 0x9c + +/* Bit settings for SMI_CTL */ +#define SMI_CTL_SET_DISABLE (0b00) +#define SMI_CTL_SET_SMI (0b01) +#define SMI_CTL_SET_NMI (0b10) +#define SMI_CTL_SET_IRQ13 (0b11)
#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 + +#define SMI_REG_SMICTRL2 0xa8 /* SMIs reported in SMIx84 */ +#define SMICTRL2_FAKE2_SMI_EN (SMI_CTL_SET_SMI << 6) +#define SMICTRL2_FAKE1_SMI_EN (SMI_CTL_SET_SMI << 4) +#define SMICTRL2_FAKE0_SMI_EN (SMI_CTL_SET_SMI << 2) + +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc + +#define SMI_REG_SMICTRL8 0xc0 /* SMIs reported in SMIx90 */ +#define SMICTRL8_FAKE2_SMI_EN (SMI_CTL_SET_SMI << 24) +#define SMICTRL8_FAKE1_SMI_EN (SMI_CTL_SET_SMI << 22) +#define SMICTRL8_FAKE0_SMI_EN (SMI_CTL_SET_SMI << 20) + +#define SMI_REG_SMICTRL9 0xc4 /* SMIs reported in SMIx90 */ +#define SMICTRL9_MTRAP_EN (SMI_CTL_SET_SMI << 16) /* Enable memory trap SMI */ +#define SMICTRL9_MTRAP_MASK (0x03 << 16) /* Memory trap field mask */ +#define SMI_REG_IO_TRAP0 0xc8 +#define SMI_REG_MEM_TRAP0 0xd0 +#define SMI_REG_MEM_RD_OVR_DATA 0xd4 +#define SMI_REG_CFG_TRAP0 0xf0
enum smi_mode { SMI_MODE_DISABLE = 0, @@ -54,6 +150,8 @@ write16((void *)(SMI_BASE + offset), value); }
+void smm_southbridge_clear_state(void); + void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void disable_gevent_smi(uint8_t gevent); void enable_acpi_cmd_smi(void); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 9aff690..9865191 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -9,6 +9,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <delay.h> +#include <amdblocks/psp_smm.h> #include <soc/smi.h> #include <soc/southbridge.h>
@@ -105,10 +106,37 @@ { const uint32_t status = smi_read32(0x90);
+ /* Check for PSP mailbox initialization */ + if (status & SMISTAT4_MEMTRAP_EVT) { + psp_smm_init(status); + } + + /* Check for PSP mailbox event */ + if (status & SMISTAT4_FAKESMI_0) + psp_p2cmbox_event(status); + /* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x90, status); }
+void smm_southbridge_clear_state(void) +{ + uint32_t reg = smi_read32(SMI_REG_GPESTAT); + smi_write32(SMI_REG_GPESTAT, reg); + + reg = smi_read32(SMI_REG_SMISTAT0); + smi_write32(SMI_REG_SMISTAT0, reg); + + reg = smi_read32(SMI_REG_SMISTAT1); + smi_write32(SMI_REG_SMISTAT1, reg); + + reg = smi_read32(SMI_REG_SMISTAT2); + smi_write32(SMI_REG_SMISTAT2, reg); + + reg = smi_read32(SMI_REG_SMISTAT4); + smi_write32(SMI_REG_SMISTAT4, reg); +} + void southbridge_smi_handler(void) { const uint16_t smi_src = smi_read16(0x94);
-
frank vibrans (Code Review)