New patch to review for coreboot: cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16901

-gerrit

commit 61a007ec0defdf9e954e1ddb67b97bf4945526b9
Author: Arthur Heymans 
Date:   Thu Oct 6 12:14:14 2016 +0200

cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E

The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo
    Processor on 65 nm Process" mentions cpu C-states substates which can
    either be atteined by adding a substate hint to the MWAIT/P_LVLx request
    or automatically by setting some msr bits correctly.

This just sets the same msr bits as model_6fx to enable dynamic L2 cache,
    C2E and C4E acpi cpu states.

The results is that when limiting a thinkpad x60 with a yonah T2400
    cpu to the acpi cpu C2 state, the idle power usage drops from 18W to 14W. When
    the lowest C-state is set to C4 the idle power usage seems to remain similar.

Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3
    Signed-off-by: Arthur Heymans 
---
 src/cpu/intel/model_6ex/model_6ex_init.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 91633ec..d42ff69 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -69,7 +69,7 @@ static void configure_c_states(void)
    msr.lo |= (1 << 15); // config lock until next reset.
    msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
    msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
+	msr.lo |= (1 << 3); //dynamic L2

/* Number of supported C-States */
    msr.lo &= ~7;
@@ -103,7 +103,13 @@ static void configure_misc(void)
    // TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
    msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */

-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
+	/* Enable C2E */
+	msr.lo |= (1 << 26);
+
+	/* Enable C4E */
+	msr.hi |= (1 << (32 - 32)); // C4E
+	msr.hi |= (1 << (33 - 32)); // Hard C4E
+
    wrmsr(IA32_MISC_ENABLE, msr);

msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */