[M] Change in coreboot[master]: mb/google/brya: Add romstage early graphics for brya and skolas

[Jérémy Compostella (Code Review)]

Attention is currently required from: Tarun Tuli.

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70304 )

Change subject: mb/google/brya: Add romstage early graphics for brya and skolas
......................................................................

mb/google/brya: Add romstage early graphics for brya and skolas

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=TO-BE-COMPLETED

Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513
Signed-off-by: Jeremy Compostella 
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Makefile.inc
A src/mainboard/google/brya/gma-mainboard.ads
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
5 files changed, 48 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/70304/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1fb78c0..af4ff3b 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -47,6 +47,7 @@
    select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_CR50
+	select MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT

config BOARD_GOOGLE_BASEBOARD_BRASK
    def_bool n
@@ -87,6 +88,7 @@
    select SOC_INTEL_RAPTORLAKE
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_CR50
+	select MAINBOARD_HAS_ROMSTAGE_LIBGFXINIT

if BOARD_GOOGLE_BRYA_COMMON

diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc
index c40f21c..74ad82f 100644
--- a/src/mainboard/google/brya/Makefile.inc
+++ b/src/mainboard/google/brya/Makefile.inc
@@ -20,3 +20,5 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+romstage-$(CONFIG_MAINBOARD_USE_ROMSTAGE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/google/brya/gma-mainboard.ads b/src/mainboard/google/brya/gma-mainboard.ads
new file mode 100644
index 0000000..eaaaa42
--- /dev/null
+++ b/src/mainboard/google/brya/gma-mainboard.ads
@@ -0,0 +1,10 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+private package GMA.Mainboard is
+   ports : constant Port_List :=
+     (eDP,
+      others => Disabled);
+end GMA.Mainboard;
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 70e7779..f9e58a7 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -123,7 +123,16 @@
    }"

device domain 0 on
-		device ref igpu on end
+		device ref igpu on
+			# Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000
+			register "panel_cfg" = "{
+			    .up_delay_ms        = 200,
+			    .down_delay_ms        = 50,
+			    .cycle_delay_ms        = 500,
+			    .backlight_on_delay_ms    = 1,
+			    .backlight_off_delay_ms = 200,
+			    .backlight_pwm_hz          = 200,}"
+		end
    	device ref dtt on end
    	device ref tbt_pcie_rp0 on end
    	device ref tbt_pcie_rp1 on end
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
index 6ca0c9e..5c5c2d1 100644
--- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
@@ -127,7 +127,16 @@
    }"

device domain 0 on
-		device ref igpu on end
+		device ref igpu on
+			# Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000
+			register "panel_cfg" = "{
+			    .up_delay_ms        = 200,
+			    .down_delay_ms        = 50,
+			    .cycle_delay_ms        = 500,
+			    .backlight_on_delay_ms    = 1,
+			    .backlight_off_delay_ms = 200,
+			    .backlight_pwm_hz          = 200,}"
+		end
    	device ref dtt on end
    	device ref tbt_pcie_rp0 on end
    	device ref tbt_pcie_rp1 on end