[M] Change in coreboot[master]: mb/intel/mtlrvp: Describe TCSS USB ports

[Harsha B R (Code Review)]

Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P.

Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/72785

to look at the new patch set (#4).

Change subject: mb/intel/mtlrvp: Describe TCSS USB ports
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mb/intel/mtlrvp: Describe TCSS USB ports

This patch describes the TCSS USB ports for mtlrvp as per schematics.
This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below,
tcss_usb3_port1: USB3 Type-C Port C0
tcss_usb3_port2: USB3 Type-C Port C1
tcss_usb3_port3: USB3 Type-C Port C2
tcss_usb3_port4: USB3 Type-C Port C3

BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration
of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C
ports as part of cbmem -c.

Signed-off-by: Harsha B R 
Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0
Signed-off-by: Jamie Ryu 
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 54 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/72785/4