[S] Change in coreboot[master]: mb/google/nissa/var/uldren: Add DPTF parameters

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75413?usp=email )

Change subject: mb/google/nissa/var/uldren: Add DPTF parameters
......................................................................

mb/google/nissa/var/uldren: Add DPTF parameters

The DPTF parameters were verified by the thermal team.

BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243
Signed-off-by: Dtrain Hsu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Sumeet R Pawnikar 
---
M src/mainboard/google/brya/variants/uldren/overridetree.cb
1 file changed, 49 insertions(+), 0 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified
  Sumeet R Pawnikar: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb
index 6f54e69..77b86552 100644
--- a/src/mainboard/google/brya/variants/uldren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb
@@ -159,6 +159,55 @@
    }"

device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""CPU_VR""
+				register "options.tsr[1].desc" = ""Charger""
+				register "options.tsr[2].desc" = ""Ambient""
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 85, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 5000),
+				}"
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      98, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      98, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      98, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 3000,
+						.max_power = 6000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 250
+					},
+					.pl2 = {
+						.min_power = 25000,
+						.max_power = 25000,
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 1000
+					}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+				device generic 0 on end
+			end
+		end
    	device ref cnvi_wifi on
    		chip drivers/wifi/generic
    			register "wake" = "GPE0_PME_B0"