Change in coreboot[master]: [WIP, NOTFORMERGE]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/23496

to look at the new patch set (#2).

Change subject: [WIP,NOTFORMERGE]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................

[WIP,NOTFORMERGE]nb/intel/i945: Use C_ENVIRONMENT_BOOTBLOCK

When the rom is cached in bootblock, ramstage currently fails to
run properly. If no mtrr covers the ROM it boots fine, but ofc
romstage will be terribly slow...

Change-Id: I4a301c47f058b119f692ee1cff2e43414281a861
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/car/Makefile.inc
A src/cpu/intel/car/bootblock.c
M src/cpu/intel/car/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/car/teardown_car.S
M src/cpu/intel/common/Kconfig
M src/cpu/intel/common/Makefile.inc
A src/cpu/intel/common/util.c
A src/cpu/intel/common/util.h
M src/cpu/intel/socket_441/Kconfig
M src/mainboard/intel/d945gclf/Makefile.inc
A src/mainboard/intel/d945gclf/bootblock.c
M src/mainboard/intel/d945gclf/romstage.c
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/i945/ram_calc.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/superio/smsc/lpc47m15x/Makefile.inc
19 files changed, 426 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23496/2