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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51717 )
Change subject: soc/intel/fsp_broadwell_de: Set up LPC Generic Memory Range register
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Patch Set 2: Code-Review+1
(2 comments)
Patchset:
PS2:
Looks much better, thanks! Just one last nit.
File src/soc/intel/fsp_broadwell_de/southcluster.c:
https://review.coreboot.org/c/coreboot/+/51717/comment/77124e9d_8fb99c93
PS2, Line 224: res->base = config->lpc_lgmr;
You should mask the enable bit:
res->base = config->lpc_lgmr & ~1;
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