Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60801 )
Change subject: soc/intel/common/gpio: Perform GPIO PAD lock outside SMM ......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60801/comment/c5c2a301_e8d21233 PS1, Line 9: This patch performs GPIO PAD lock configuration in non-smm : mode. Typically, coreboot enables SMI at latest boot phase : post FSP-S, hence, FSP-S might get chance to perform GPP lock : configuration. With this code changes, coreboot can be able to : perform GPIO PAD lock configuration early in the boot flow, : prior to calling FSP-S.
Please reflow for 72 characters per line.
Ack
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/60801/comment/bf6d33d4_96145367 PS1, Line 569:
Can we do a check for BIOS_DONE. […]
@Tim, can you please help me to understand your comment above.
This is what I understood: You are asking to check if MSR(0x151) bit 0 (ENABLE_IA_UNTRUSTED) is set or not? if not set then coreboot returns -1 and exit from here. is that what you meant ?
But looks like BIOS_DONE MSR 0x151 is being set as part of FSP-S doing CPU feature programming (SetBiosDone Start) hence, prior to that, BIT 0 would always return `0` and we won't be able to perform GPP lock using this function (outside SMM). Note: this function might get called from coreboot gpio programming prior to FSP-S being call.
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Subrata Banik (Code Review)