Patch set updated for coreboot: google/gru: Tune USB 2.0 PHY to increase compatibility

[Martin Roth]

Martin Roth ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17566

-gerrit

commit 3f24a27336aaeb40d4b9170ea0458a7d0cad5b2e
Author: William wu 
Date:   Thu Nov 10 19:34:45 2016 +0800

google/gru: Tune USB 2.0 PHY to increase compatibility

When testing USB 2.0 compatibility with different kinds
    of USB 2.0 devices on Kevin board, we find that some
    USB HDDs (e.g. seagate SRD00F1 1TB HDD) and some smart
    phones (e.g. galaxy A5 smart phone) can't be detected.
    And according to the error log, this issue is related
    to USB 2.0 PHY signal problem.

For the USB HDD, error log is:
    [  592.557724] usb 5-1: new high-speed USB device number 2 using xhci-hcd
    [  592.847735] usb 5-1: new high-speed USB device number 3 using xhci-hcd
    [  593.473720] usb 5-1: new high-speed USB device number 6 using xhci-hcd
    [  594.187717] usb 5-1: new high-speed USB device number 9 using xhci-hcd
    [  595.020717] usb 5-1: new high-speed USB device number 13 using xhci-hcd
    [  595.284730] usb 5-1: new high-speed USB device number 14 using xhci-hcd
    [  595.574816] usb 5-1: new high-speed USB device number 15 using xhci-hcd

The log shows that HDD failed to high-speed handshake.

For the smart phone, error log is:
    [ 1145.661625] usb 5-1: new high-speed USB device number 2 using xhci-hcd
    [ 1145.771674] usb 5-1: device descriptor read/64, error -71
    [ 1145.979752] usb 5-1: device descriptor read/64, error -71
    [ 1146.187721] usb 5-1: new high-speed USB device number 3 using xhci-hcd
    [ 1146.301754] usb 5-1: device descriptor read/64, error -71
    [ 1146.509750] usb 5-1: device descriptor read/64, error -71
    [ 1146.717722] usb 5-1: new high-speed USB device number 4 using xhci-hcd
    [ 1146.724393] usb 5-1: Device not responding to setup address.
    [ 1146.930795] usb 5-1: Device not responding to setup address.
    [ 1147.137720] usb 5-1: device not accepting address 4, error -71
    [ 1147.246644] usb 5-1: new high-speed USB device number 5 using xhci-hcd
    [ 1147.253336] usb 5-1: Device not responding to setup address.
    [ 1147.459786] usb 5-1: Device not responding to setup address.
    [ 1147.665712] usb 5-1: device not accepting address 5, error -71
    [ 1147.671789] usb usb5-port1: unable to enumerate USB device

The log shows that smart phone failed to read device
    descriptor, error -71 may be caused by PHY signal problem.

This patch aims to tune USB 2.0 PHY with the following
    parameters to support USB HDD, smart phone and some other
    potential USB 2.0 devices.

1. Disable the pre-emphasize in chirp state to avoid
       high-speed handshake failure.

2. Bypass ODT auto compensation to enable set max driver
       strength manually. (Bit[42] of usbphy_ctrl register is
       1'b1 for bypass, and Bit[41:37] of usbphy_ctrl register
       is 5'b10000 for max driver strength).

3. Bypass ODT auto refresh, and set the max bias current
       tuning reference. (Bit[57] of usbphy_ctrl register is
       1'b1 for bypass, and Bit[52:50] of usbphy_ctrl register
       is 3b'100  for max bias current tuning reference).

We have done the USB 2.0 compliance test and compatibility test
    with this patch, it works well.

BRANCH=gru
    BUG=chrome-os-partner:59623
    TEST=plug/unplug USB HDD or smart phone in Type-C port,
    check if they can be detected successfully.

Change-Id: I275c2236b8e469bfd04e9184d007eb095657225e
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 7735c514d4136978133c2299f2f58da8320bb89f
    Original-Change-Id: I4e6c10faa1c03af9880a89afe4731a7065eb1e4e
    Original-Signed-off-by: William wu 
    Original-Reviewed-on: https://chromium-review.googlesource.com/409856
    Original-Commit-Ready: Eddie Cai 
    Original-Tested-by: Cindy Han 
    Original-Reviewed-by: Julius Werner 
---
 src/mainboard/google/gru/mainboard.c | 40 ++++++++++++++++++++++++++----------
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index d34a9f7..7e360e7 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -235,18 +235,36 @@ static void setup_usb(void)
    /* A few magic PHY tuning values that improve eye diagram amplitude
     * and make it extra sure we get reliable communication in firmware. */
    /* Set max ODT compensation voltage and current tuning reference. */
-	write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3);
-	write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3);
-	/* Set max pre-emphasis level, only on Kevin PHY0 and PHY1,
-	 * and disable the pre-emphasize in eop state to avoid
-	 * mis-trigger the disconnect detection. */
+	write32(&rk3399_grf->usbphy0_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
+	write32(&rk3399_grf->usbphy1_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
+
    if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) {
-		write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7);
-		write32(&rk3399_grf->usbphy1_ctrl[12], 0xffff00a7);
-		write32(&rk3399_grf->usbphy0_ctrl[0], 0x00010000);
-		write32(&rk3399_grf->usbphy1_ctrl[0], 0x00010000);
-		write32(&rk3399_grf->usbphy0_ctrl[13], 0x00010000);
-		write32(&rk3399_grf->usbphy1_ctrl[13], 0x00010000);
+		/* Set max pre-emphasis level, only on Kevin PHY0 and PHY1 */
+		write32(&rk3399_grf->usbphy0_ctrl[12],
+			RK_CLRSETBITS(0xffff, 0xa7));
+		write32(&rk3399_grf->usbphy1_ctrl[12],
+			RK_CLRSETBITS(0xffff, 0xa7));
+
+		/* Disable the pre-emphasize in eop state and chirp
+		 * state to avoid mis-trigger the disconnect detection
+		 * and also avoid high-speed handshake fail */
+		write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3));
+		write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3));
+		write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3));
+		write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3));
+
+		/* ODT auto compensation bypass, set max driver strength */
+		write32(&rk3399_grf->usbphy0_ctrl[2],
+			RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
+		write32(&rk3399_grf->usbphy1_ctrl[2],
+			RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
+
+		/* ODT auto refresh bypass, and set the max
+		 * bias current tuning reference */
+		write32(&rk3399_grf->usbphy0_ctrl[3],
+			RK_CLRSETBITS(0x21c, 1 << 4));
+		write32(&rk3399_grf->usbphy1_ctrl[3],
+			RK_CLRSETBITS(0x21c, 1 << 4));
    }

setup_usb_otg0();