Ionela Voinescu (ionela.voinescu@imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12763
-gerrit
commit 9b552bfe7e6a5d6b704b381222c56b26b354398d Author: Ionela Voinescu ionela.voinescu@imgtec.com Date: Thu May 21 13:29:45 2015 +0100
imgtec/pistachio: DDR2, DDR3: DQS gate early
Switching on DQS Gate Early and DQS Gate Extension with 500R DQS/DSQN Resistors. This setup was recommended by Synopsys.
Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly.
Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3 Signed-off-by: Ionela Voinescu ionela.voinescu@imgtec.com --- src/soc/imgtec/pistachio/ddr2_init.c | 16 +++++++++++----- src/soc/imgtec/pistachio/ddr3_init.c | 16 +++++++++++----- src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h | 3 +++ 3 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index e21b79b..322d241 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -143,8 +143,8 @@ int init_ddr2(void) * 2 ZUEN Def 1 * 3 LPIOPD DEf 1 0 * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention 000 - * 10:8 DQSGE DQS Early Gate + * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys + * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys * 11 NOBUB No Bubbles, adds latency 1 * 12 FXDLAT Fixed Read Latency 0 * 15:13 Reserved @@ -159,7 +159,9 @@ int init_ddr2(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000807); + write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); + /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ + write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 2 * 4:2 tRTP 3 @@ -235,6 +237,10 @@ int init_ddr2(void) /* PGSR : Wait for DRAM Init Done */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) return DDR_TIMEOUT; + /* Disable Impedance Calibration */ + write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); + write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); + /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, 0x00000001)) @@ -315,10 +321,10 @@ int init_ddr2(void) * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 */ write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /*TRTW : Read to Write turn around time Def 2 + /*TRTW : Read to Write turn around time Def 3 * Actual gap t_bl + t_rtw */ - write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000002); + write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); /* TCKE : CKE min pulse width DEf 3 */ write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); /* diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c index 0a5a444..e77a5cd 100644 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ b/src/soc/imgtec/pistachio/ddr3_init.c @@ -163,8 +163,8 @@ int init_ddr3(void) * 2 ZUEN Def 1 * 3 LPIOPD DEf 1 0 * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention 000 - * 10:8 DQSGE DQS Early Gate + * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys + * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys * 11 NOBUB No Bubbles, adds latency 1 * 12 FXDLAT Fixed Read Latency 0 * 15:13 Reserved @@ -179,7 +179,9 @@ int init_ddr3(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000807); + write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927); + /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ + write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 0 * 4:2 tRTP 2 @@ -333,10 +335,10 @@ int init_ddr3(void) * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 */ write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /* TRTW : Read to Write turn around time Def 2 + /* TRTW : Read to Write turn around time Def 3 * Actual gap t_bl + t_rtw */ - write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000002); + write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); /* TCKE : CKE min pulse width DEf 3 */ write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); /* TXPDLL : Slow Exit Power Down to first valid cmd delay @@ -498,6 +500,10 @@ int init_ddr3(void) /* STAT : Wait for Switch INIT to Config State */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F)) return DDR_TIMEOUT; + /* Disable Impedance Calibration */ + write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); + write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); + /* SCTL : UPCTL switch Config to ACCESS State */ write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); /* STAT : Wait for switch CFG -> GO State */ diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h index a0f661b..a9d18a0 100644 --- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h +++ b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h @@ -103,6 +103,7 @@ #define DDRPHY_DLLGCR_OFFSET (0x0010) #define DDRPHY_PTR0_OFFSET (0x0018) #define DDRPHY_PTR1_OFFSET (0x001C) +#define DDRPHY_DXCCR_OFFSET (0x0028) #define DDRPHY_DSGCR_OFFSET (0x002C) #define DDRPHY_DCR_OFFSET (0x0030) #define DDRPHY_DTPR0_OFFSET (0x0034) @@ -120,6 +121,8 @@ #define DDRPHY_BISTAR2_OFFSET (0x011C) #define DDRPHY_BISTUDPR_OFFSET (0x0120) #define DDRPHY_BISTGSR_OFFSET (0x0124) +#define DDRPHY_ZQ0CR0_OFFSET (0x0180) +#define DDRPHY_ZQ1CR0_OFFSET (0x0190)
#define DDR_TIMEOUT_VALUE_US 100000
-
Ionela Voinescu