Attention is currently required from: Furquan Shaikh, Subrata Banik, Arthur Heymans, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56717 )
Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 5: Code-Review+1
(2 comments)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/56717/comment/42343a95_1e3db433
PS5, Line 71: is used to control with one bit of SF QoS register
suggestion:
`are controlled by one bit of the SF QoS register`
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56717/comment/6c2820ac_88f48bc2
PS5, Line 540: mov %eax, %ebx /* back up IA32_CR_SF_QOS_MASK_2 in ebx */
nit: should this go in the next patch?
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