Michael Büchler has uploaded this change for review.
mb/asrock/h77pro4-m: add new mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro4-M which is already supported by coreboot.
Working:
- Console output on the serial port of the Super I/O
- Native RAM initialization with two DIMMs
- Core i5-2500 CPU
Not working:
- Currently fails during PCIe bus scans
Untested:
- Ivy Bridge
- All four DIMM slots
- The rest
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
---
A src/mainboard/asrock/h77pro4-m/Kconfig
A src/mainboard/asrock/h77pro4-m/Kconfig.name
A src/mainboard/asrock/h77pro4-m/Makefile.inc
A src/mainboard/asrock/h77pro4-m/acpi/ec.asl
A src/mainboard/asrock/h77pro4-m/acpi/platform.asl
A src/mainboard/asrock/h77pro4-m/acpi/superio.asl
A src/mainboard/asrock/h77pro4-m/acpi_tables.c
A src/mainboard/asrock/h77pro4-m/board_info.txt
A src/mainboard/asrock/h77pro4-m/devicetree.cb
A src/mainboard/asrock/h77pro4-m/dsdt.asl
A src/mainboard/asrock/h77pro4-m/early_init.c
A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads
A src/mainboard/asrock/h77pro4-m/gpio.c
A src/mainboard/asrock/h77pro4-m/hda_verb.c
A src/mainboard/asrock/h77pro4-m/mainboard.c
15 files changed, 612 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/1
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig
new file mode 100644
index 0000000..daa1526
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/Kconfig
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_ASROCK_H77PRO4_M
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select SUPERIO_NUVOTON_NCT6776
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select USE_NATIVE_RAMINIT
+ select DRIVERS_ASMEDIA_ASPM_BLACKLIST # FIXME copied from B75 Pro3M
+
+config MAINBOARD_DIR
+ string
+ default asrock/h77pro4-m
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H77 Pro4-M"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0152.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0152"
+
+#config DRAM_RESET_GATE_GPIO # FIXME: check this
+# int
+# default 60
+#
+#config USBDEBUG_HCD_INDEX # FIXME: check this
+# int
+# default 2
+endif
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig.name b/src/mainboard/asrock/h77pro4-m/Kconfig.name
new file mode 100644
index 0000000..03873b9
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASROCK_H77PRO4_M
+ bool "H77 Pro4-M"
diff --git a/src/mainboard/asrock/h77pro4-m/Makefile.inc b/src/mainboard/asrock/h77pro4-m/Makefile.inc
new file mode 100644
index 0000000..a0d1155
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/h77pro4-m/acpi/ec.asl b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/asrock/h77pro4-m/acpi/platform.asl b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl
new file mode 100644
index 0000000..146be65
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Method(_WAK, 1)
+{
+ Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/asrock/h77pro4-m/acpi/superio.asl b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl
new file mode 100644
index 0000000..1eae4b2
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+
+#define NCT6776_SHOW_SP1 1
+#define NCT6776_SHOW_KBC 1
+
+#include "superio/nuvoton/nct6776/acpi/superio.asl"
diff --git a/src/mainboard/asrock/h77pro4-m/acpi_tables.c b/src/mainboard/asrock/h77pro4-m/acpi_tables.c
new file mode 100644
index 0000000..f8364ab
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/asrock/h77pro4-m/board_info.txt b/src/mainboard/asrock/h77pro4-m/board_info.txt
new file mode 100644
index 0000000..5f86088d
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb
new file mode 100644
index 0000000..8c5d0e5
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ #register "gfx.use_spread_spectrum_clock" = "0" # from B75 Pro3-M
+ #register "gfx" = "GMA_STATIC_DISPLAYS(0)" # from autoport
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "0"
+ register "gpu_panel_power_backlight_on_delay" = "0"
+ register "gpu_panel_power_cycle_delay" = "4"
+ register "gpu_panel_power_down_delay" = "0"
+ register "gpu_panel_power_up_delay" = "0"
+ register "gpu_pch_backlight" = "0x00000000"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1849 0x0100
+ end
+ device pci 01.0 off # PEG
+ end
+ device pci 02.0 on # iGPU
+ subsystemid 0x1849 0x0102
+ end
+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0291"
+ register "gen2_dec" = "0x000c0241"
+ register "gen3_dec" = "0x000c0251"
+ register "gen4_dec" = "0x00000000"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "0"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x1849 0x1e31
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x1849 0x1e3a
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1849 0x1e2d
+ end
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1849 0x8892
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x1849 0x1e10
+ end
+ device pci 1c.1 off # PCIe Port #2
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE
+ subsystemid 0x1849 0x1e1a
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller
+ subsystemid 0x1849 0x1e1e
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1849 0x1e26
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x1849 0x1e4a
+ chip superio/nuvoton/nct6776
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # Parallel port
+ # TODO verify
+ # global
+ irq 0x1c = 0x80
+ irq 0x27 = 0xc0
+ irq 0x2a = 0x62
+ # parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 5
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2, IR
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO6-9
+ device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA
+ device pnp 2e.9 off end # GPIO2-5
+ device pnp 2e.a on # ACPI
+ # TODO verify
+ irq 0xe0 = 0x01
+ irq 0xe3 = 0x14
+ irq 0xe6 = 0x4c
+ #irq 0xe9 = 0x02
+ irq 0xf0 = 0x20
+ end
+ device pnp 2e.b off end # HWM, front panel LED
+ device pnp 2e.d on end # VID
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f on end # GPIO Push-Pull or Open-drain
+ device pnp 2e.14 on end # SVID
+ device pnp 2e.16 on end # Deep Sleep
+ device pnp 2e.17 on end # GPIOA
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1849 0x1e02
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1849 0x1e22
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ end
+end
diff --git a/src/mainboard/asrock/h77pro4-m/dsdt.asl b/src/mainboard/asrock/h77pro4-m/dsdt.asl
new file mode 100644
index 0000000..38f5325
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c
new file mode 100644
index 0000000..ca79de8
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/early_init.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+#include <superio/nuvoton/common/nuvoton.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Set GPIOs on superio, enable UART */
+ nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+ pnp_set_logical_device(SERIAL_DEV);
+
+ pnp_write_config(SERIAL_DEV, 0x1b, 0x68); // bit 4 now cleared -> pin 95 GP24
+ pnp_write_config(SERIAL_DEV, 0x1c, 0x80); // Pin 54 AFD#, pin 55 STB#
+ // default 0x64, vendor BIOS 0x5c
+ // bit 3 '1' -> CPUFANOUT push-pull instead of open drain
+ // bit 4 '1' -> SYSFANOUT push-pull instead of open drain
+ // bit 5 '0' -> AUXFANOUT open drain instead of push-pull
+ pnp_write_config(SERIAL_DEV, 0x24, 0x5c); // Pin 88-93 GP75-GP70, Pin 86-87 GP77-76
+ pnp_write_config(SERIAL_DEV, 0x27, 0xc0); // Pin 88-93 GP75-GP70, Pin 86-87 GP77-76
+ // default 0xc0 (bits 7,6 set), vendor BIOS 0x62 (bit 7 cleared, bit 1 set)
+ // bit 7 is '0' --> pins 29-36 COM A instead of GPIO8 (GP8*)
+ // bit 6 is '1' --> pins 116-123 are VIDI[7-0]
+ // bit 1 is '1' --> pin 56,57 are GP23,22 instead of MCLK,MDAT
+ // bit 0 is '0' --> pins 58,59 stay as KCLK,KDAT
+ pnp_write_config(SERIAL_DEV, 0x2a, 0x62); // Pin 29-36 COM A
+ pnp_write_config(SERIAL_DEV, 0x2b, 0x08); // Pin 81 GP32 instead of CPUPWRGD
+ pnp_write_config(SERIAL_DEV, 0x2c, 0x80); // Pin 113,115 GPA0,PECI instead of TSIC,TSID
+
+ // FIXME 0x13,0x14 "Device IRQ Polarity Selection" are set by the vendor BIOS
+
+ /* random note
+ * 24M_48M_SEL strap can be read on config reg 0x2f bit 0, it's '1' -> 48 MHz
+ * also LPT_EN is '1' on bit 1 of 0x2f -> LPT enabled
+ */
+
+ nuvoton_pnp_exit_conf_state(SERIAL_DEV);
+
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ // generated by autoport
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1405);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+}
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads
new file mode 100644
index 0000000..133fde5
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads
@@ -0,0 +1,23 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ LVDS,
+ eDP);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asrock/h77pro4-m/gpio.c b/src/mainboard/asrock/h77pro4-m/gpio.c
new file mode 100644
index 0000000..84f4564
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/gpio.c
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c
new file mode 100644
index 0000000..9998266
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */
+ 0x18498892, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x18498892),
+ AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19950),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214120),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/h77pro4-m/mainboard.c b/src/mainboard/asrock/h77pro4-m/mainboard.c
new file mode 100644
index 0000000..4322c1e
--- /dev/null
+++ b/src/mainboard/asrock/h77pro4-m/mainboard.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
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