Patrick Georgi merged this change.
soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register
Currently all the helpers support configuring GPIO_DW0/1 registers. In
some architectures there is an additional configuration GPIO_DW2 register
that can be used to configure debounce duration etc. Add a helper macro
to enable configuring GPIO_DW2 pad register.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the current
configuration is not disturbed by turning on the GPIO_DEBUG option and
verifying the debug output before and after the change.
Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index 418b6ab..6aeef04 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -145,6 +145,19 @@
.pad_config[1] = __config1, \
}
+#if GPIO_NUM_PAD_CFG_REGS > 2
+#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
+ { \
+ .pad = __pad, \
+ .pad_config[0] = __config0, \
+ .pad_config[1] = __config1, \
+ .pad_config[2] = __config2, \
+ }
+#else
+#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
+ _PAD_CFG_STRUCT(__pad, __config0, __config1)
+#endif
+
/* Native function configuration */
#define PAD_CFG_NF(pad, pull, rst, func) \
_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
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