[coreboot-gerrit] Change in coreboot[master]: mb/emulation/spike-riscv: Update UART address

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/20126

Change subject: mb/emulation/spike-riscv: Update UART address
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mb/emulation/spike-riscv: Update UART address

I updated my spike patch[1] to cleanly apply to current spike master.
As a side effect, the UART is now at 0x02100000.

[1]: https://github.com/riscv/riscv-isa-sim/pull/53

Change-Id: I4cb09014619e230011486fa57636abe183baa4be
Signed-off-by: Jonathan Neuschäfer 
---
M src/mainboard/emulation/spike-riscv/uart.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/20126/1

diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c
index 57647fe..26ab630 100644
--- a/src/mainboard/emulation/spike-riscv/uart.c
+++ b/src/mainboard/emulation/spike-riscv/uart.c
@@ -20,5 +20,5 @@

uintptr_t uart_platform_base(int idx)
 {
-	return (uintptr_t) 0x40001000;
+	return (uintptr_t) 0x02100000;
 }