[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31284 )

Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML
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Patch Set 16:

(1 comment)

https://review.coreboot.org/#/c/31284/15/src/soc/intel/cannonlake/include/so... 
File src/soc/intel/cannonlake/include/soc/serialio.h:

https://review.coreboot.org/#/c/31284/15/src/soc/intel/cannonlake/include/so... 
PS15, Line 35: #endif
> What about PchSerialIoLegacyUart then? does it do the same […]

PchSerialIoLegacyUart was introduced from CML FSP code and it is used to communicate to FSP that UART port should be used as a Legacy UART and not in LPSS mode. 
Note that value of enum is different because FSP code base is different across CNL and CML platforms. Since FSP code itself has change in enum value, coreboot need to keep that in sync with FSP.