Subrata Banik has uploaded this change for review.
soc/intel/common/block/cpu: Use tab instead of space
Convert the lines starts with whitespace with tab as applicable.
Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/51375/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 614cd9a1b..3febe97 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -398,15 +398,15 @@
* Then we need to allocate just one way for non-eviction
* of RW data.
*/
- movl $0x01, %eax
- cmp $CONFIG_DCACHE_RAM_SIZE, %ecx
- jnc set_eviction_mask
+ movl $0x01, %eax
+ cmp $CONFIG_DCACHE_RAM_SIZE, %ecx
+ jnc set_eviction_mask
/*
* RW data size / way size is equal to number of
* ways to be configured for non-eviction
*/
- mov $CONFIG_DCACHE_RAM_SIZE, %eax
+ mov $CONFIG_DCACHE_RAM_SIZE, %eax
div %ecx
mov %eax, %ecx
movl $0x01, %eax
@@ -440,11 +440,11 @@
* - If this bit is '0' - the way is protected from eviction
* - If this bit is '1' - the way is not protected from eviction
*/
- mov $0x1, %eax
- shl %cl, %eax
- subl $0x01, %eax
- mov %eax, %ecx
- mov %ebx, %eax
+ mov $0x1, %eax
+ shl %cl, %eax
+ subl $0x01, %eax
+ mov %eax, %ecx
+ mov %ebx, %eax
xor $~0, %eax /* invert 32 bits */
and %ecx, %eax
To view, visit change 51375. To unsubscribe, or for help writing mail filters, visit settings.