Angel Pons submitted this change.
sb/intel: Remove inexistent references to IDE controller
This device doesn't exist on these southbridges.
Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/lynxpoint/pch.h
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index b7842c0..7552906 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -155,8 +155,7 @@
#define LGMR 0x98 /* LPC Generic Memory Range */
#define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */
-/* PCI Configuration Space (D31:F1): IDE */
-#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
+/* PCI Configuration Space (D31:F2): SATA */
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 7c2e2a9..76d0ad6 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -148,8 +148,7 @@
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
-/* PCI Configuration Space (D31:F1): IDE */
-#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
+/* PCI Configuration Space (D31:F2): SATA */
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define INTR_LN 0x3c
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 9946944..893bfde 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -212,8 +212,7 @@
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LGMR 0x98 /* LPC Generic Memory Range */
-/* PCI Configuration Space (D31:F1): IDE */
-#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
+/* PCI Configuration Space (D31:F2): SATA */
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define INTR_LN 0x3c
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