CK HU would like Duan huayang to review this change.
soc/mediatek/mt8192: Set dramc DVFS setting
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I3750a52046b241e533873aee1e6061c65e4bbea3
---
M src/soc/mediatek/mt8192/dramc_dvfs.c
M src/soc/mediatek/mt8192/dramc_pi_basic_api.c
2 files changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44726/1
diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c
index c51c261..eb37ac3 100644
--- a/src/soc/mediatek/mt8192/dramc_dvfs.c
+++ b/src/soc/mediatek/mt8192/dramc_dvfs.c
@@ -111,6 +111,63 @@
*(cali->pll_mode) = pll_mode;
}
+void dvfs_settings(const struct ddr_cali *cali)
+{
+ u32 bc_bak = dramc_get_broadcast();
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel,
+ MISC_CKMUX_SEL_RG_52M_104M_SEL, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_dvfsdll,
+ MISC_SHU_DVFSDLL_R_DLL_IDLE, 0x2b,
+ MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 0x43);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
+ MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, get_shu(cali));
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
+ MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
+ MISC_DVFSCTL2_RG_MRW_AFTER_DFS, 1);
+ SET32_BITFIELDS(&mtk_dpm->fsm_cfg_1,
+ LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 1,
+ LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 1,
+ LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 1,
+ LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_opt,
+ MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 1,
+ MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
+ MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 1,
+ MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl7,
+ MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl,
+ MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 1,
+ MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl,
+ MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 1,
+ MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 3,
+ MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW, 3);
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_dvfsctl2,
+ MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 0);
+ SET32_BITFIELDS(&ch[1].phy_ao.misc_dvfsctl2,
+ MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 1);
+
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfs_emi_clk,
+ MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 0);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
+ MISC_DVFSCTL2_RG_DLL_SHUFFLE, 0);
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
+ MISC_DVFSCTL2_R_DVFS_OPTION, 0,
+ MISC_DVFSCTL2_R_DVFS_PARK_N, 0);
+ }
+
+ dramc_set_broadcast(bc_bak);
+}
+
void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst)
{
u8 tmp;
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
index ab6b027..1d6b6c2 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
@@ -4281,6 +4281,18 @@
SHU_R0_B1_DQ0_ARPI_PBYTE_B1, wl_dqs_final_delay[rank][1]);
}
}
+
+static void dramc_enable_phy_dcm(dcm_state dcm)
+{
+ u32 bc_bak = dramc_get_broadcast();
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+
+ enable_phy_dcm_non_shuffle(dcm);
+ enable_phy_dcm_shuffle(dcm, 0);
+
+ dramc_set_broadcast(bc_bak);
+}
+
static void ddr_update_ac_timing(const struct ddr_cali *cali)
{
u8 table_idx;
@@ -4568,7 +4580,10 @@
static void dramc_init(const struct ddr_cali *cali)
{
dramc_setting(cali);
+ dramc_enable_phy_dcm(DCM_OFF);
dramc_reset_delay_chain_before_calibration();
+ dvfs_settings(cali);
+
dramc_8_phase_cal(cali);
dramc_duty_calibration(cali->params);
dramc_mode_reg_init(cali);
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