Gaggery Tsai has uploaded this change for review.
mb/google/poppy/variant/atlas: Update PL2 based on CPU sku
This patch adds a function to overwrite PL2 setting based on CPU
sku.
BUG=None
BRANCH=None
TEST=emerge-atlas coreboot chemos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
---
M src/mainboard/google/poppy/variants/atlas/Makefile.inc
A src/mainboard/google/poppy/variants/atlas/mainboard.c
2 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27765/1
diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc
index ad40bb0..06776ff 100644
--- a/src/mainboard/google/poppy/variants/atlas/Makefile.inc
+++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc
@@ -19,3 +19,4 @@
ramstage-y += gpio.c
ramstage-y += nhlt.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c
new file mode 100644
index 0000000..36b703c
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <assert.h>
+#include <baseboard/variants.h>
+#include <cbfs.h>
+#include <chip.h>
+#include <commonlib/cbfs_serialized.h>
+#include <compiler.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <drivers/intel/gma/opregion.h>
+#include <intelblocks/mp_init.h>
+#include <smbios.h>
+#include <soc/ramstage.h>
+#include <string.h>
+
+#define PL2_AML 18
+#define PL2_KBL 15
+
+static uint16_t get_dev_id(struct device *dev)
+{
+ return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+static uint32_t get_pl2(void)
+{
+ uint16_t id;
+ id = get_dev_id(SA_DEV_IGD);
+ if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R)
+ return PL2_AML;
+
+ return PL2_KBL;
+}
+
+/* Override dev tree settings per board */
+void variant_devtree_update(void)
+{
+ struct device *root = SA_DEV_ROOT;
+ config_t *cfg = root->chip_info;
+
+ /* Update PL2 based on CPU */
+ cfg->tdp_pl2_override = get_pl2();
+}
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