Attention is currently required from: Tarun Tuli, Sridhar Siricilla, Angel Pons, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71574 )
Change subject: security/intel/txt: Helper function to disable TXT
......................................................................
Patch Set 3:
(1 comment)
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/71574/comment/647418b3_8fee1df9
PS3, Line 84: 0x2e6
nit:one more tab to align with earlier line?
I guess the alignment is actually proper the line before is register bit definition.
The IA32_xxx macros are all aligned with col 33.
Please check and confirm.
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