Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35672 )
Change subject: device/pci_early: Drop some __SIMPLE_DEVICE__ use ......................................................................
Patch Set 1:
(2 comments)
Patch Set 1:
(2 comments)
I may have had a problem with PCIe x16 detection on kontron 986lcd-m if there was no delay in i945_setup_pci_express_x16(). There is a waiting in pci_bus_reset(). The use of the same wait values (10ms between, 1s after) fixed the problem.
See CB:35678 such mdelay() can be followup commit.
https://review.coreboot.org/c/coreboot/+/35672/1/src/device/pci_early.c File src/device/pci_early.c:
https://review.coreboot.org/c/coreboot/+/35672/1/src/device/pci_early.c@a31 PS1, Line 31: /
pci_bus_reset() has 10ms here
I agree there should be some minimum time secondary bus is held down, need to check specs what the value is, and fix the couple call sites that may violate it. Followup work, unless you notice I have removed such delay here somewhere.
https://review.coreboot.org/c/coreboot/+/35672/1/src/device/pci_early.c@a36 PS1, Line 36: pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
pci_bus_reset() has 1 second delay here
Right.. (long) arbitrary delay in the wrong place. After deassert of secondary reset, there should be a retry loop on accessing secondary side PCI configuration space VENDOR_ID register.
AFAICS, pci_bus_reset() is never called, unless you have HyperTransport hardware that sets reset_needed flag.